Semiconductor device having trench gate structure and method for manufacturing the semiconductor device

ABSTRACT

A semiconductor device of the present invention includes a semiconductor layer in which a gate trench is formed, a gate insulating film formed along an inner surface of the gate trench, a gate electrode that is buried in the gate trench through the gate insulating film and that has a lower electrode and an upper electrode that are separated upwardly and downwardly from each other with an intermediate insulating film between the lower electrode and the upper electrode, and a gate contact that is formed in the gate trench so as to pass through the upper electrode and through the intermediate insulating film and so as to reach the lower electrode and that electrically connects the lower electrode and the upper electrode together.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a Continuation of U.S. application Ser. No. 14/936,666, filed onNov. 9, 2015, and allowed on Sep. 28, 2016, which claimed the benefit ofpriority of Japanese application No. 2014-228459 filed on Nov. 10, 2014.The disclosures of these prior US and foreign applications areincorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a semiconductor device having a trenchgate structure and a method for manufacturing the semiconductor device.

BACKGROUND ART

Patent Document 1 (Japanese Translation of International Application No.2000-511353) discloses a trench-gate type power MOSFET that includes asemiconductor substrate in which a trench is formed, a gate embedded inthe trench, a source region formed at a surface portion of thesemiconductor substrate, a body region formed below the source region,and a drain region formed below the body region.

SUMMARY OF INVENTION

A main object of the present invention is to provide a semiconductordevice that is capable of restraining a rise in temperature in thetrench gate structure and that has excellent reliability, and is toprovide a method for manufacturing the semiconductor device.

Another object of the present invention is to provide a semiconductordevice that is capable of avoiding a complex structure and that iscapable of lowering resistance, and is to provide a method formanufacturing the semiconductor device.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic plan view of a semiconductor device according to afirst preferred embodiment of the present invention.

FIG. 2 is a perspective cross-sectional view of a region surrounded bythe broken line of a VDMIS region of FIG. 1, showing a structure of asemiconductor layer while excluding an arrangement formed on thesemiconductor layer.

FIG. 3 is a cross-sectional view taken along line shown in FIG. 2.

FIG. 4 is an enlarged cross-sectional view around a trench gatestructure shown in FIG. 3.

FIG. 5 is a schematic cross-sectional view to describe a CMIS regionshown in FIG. 1, taken along line V-V shown in FIG. 1.

FIG. 6A and FIG. 6B are flowcharts to describe one example of amanufacturing process of the VDMIS region according to the semiconductordevice of FIG. 1.

FIG. 7A to FIG. 7W are cross-sectional views to describe one example ofa manufacturing process of the VDMIS region according to thesemiconductor device of FIG. 1, corresponding to FIG. 3.

FIG. 8A to FIG. 8W are cross-sectional views to describe one example ofa manufacturing process of a CMIS region according to the semiconductordevice of FIG. 1, corresponding to FIG. 5.

FIG. 9 is a schematic cross-sectional view of a semiconductor deviceaccording to a second preferred embodiment of the present invention.

FIG. 10 is an enlarged cross-sectional view showing a trench gatestructure of a semiconductor device according to a third preferredembodiment of the present invention.

FIG. 11 is a schematic perspective cross-sectional view of asemiconductor device according to a first modification.

FIG. 12 is a schematic perspective cross-sectional view of asemiconductor device according to a second modification.

FIG. 13 is a schematic enlarged cross-sectional view showing a trenchgate structure of a semiconductor device according to a thirdmodification.

FIG. 14 is a schematic enlarged cross-sectional view showing a trenchgate structure of a semiconductor device according to a fourthmodification.

FIG. 15 is an upper-surface perspective view showing one example of asemiconductor package in which a semiconductor device according to thepresent invention and according to the modifications is mounted.

FIG. 16 is a plan view showing an internal structure of thesemiconductor package shown in FIG. 15.

FIG. 17 is a cross-sectional view taken along line XVII-XVII shown inFIG. 16.

FIG. 18 is an upper-surface perspective view showing another example ofa semiconductor package in which a semiconductor device according to thepresent invention and according to the modifications is mounted.

FIG. 19 is an undersurface perspective view of the semiconductor packageshown in FIG. 18.

FIG. 20 is a plan view showing an internal structure of thesemiconductor package shown in FIG. 18.

FIG. 21 is a cross-sectional view taken along line XXI-XXI shown in FIG.20.

DESCRIPTION OF EMBODIMENTS

A semiconductor device to achieve the aforementioned objects includes asemiconductor layer in which a gate trench is formed, a gate insulatingfilm formed along an inner surface of the gate trench, a gate electrodethat is buried in the gate trench through the gate insulating film andthat has a lower electrode and an upper electrode that are separatedupwardly and downwardly from each other with an intermediate insulatingfilm between the lower electrode and the upper electrode, and a gatecontact that is formed in the gate trench so as to pass through theupper electrode and through the intermediate insulating film and so asto reach the lower electrode and that electrically connects the lowerelectrode and the upper electrode together.

Hereinafter, let it be supposed that the term “to pass through” denotesthat a component passes through a to-be-penetrated object and then exitsfrom the object to an opposite side, and, in addition, denotes that acomponent reaches another component through a portion formed by removinga part of a to-be-penetrated object.

According to this arrangement, a trench gate structure having the gateelectrode buried in the gate trench is formed. Additionally, the gateelectrode has a split gate structure that includes the lower electrodeand the upper electrode that are separated upwardly and downwardlybetween which the intermediate insulating film is sandwiched.

A method for drawing around and connecting each of the lower and upperelectrodes to the end of the gate trench is mentioned as an example of aconnection method of the lower electrode and the upper electrode in thesplit gate structure. In this method, for example, each of the lower andupper electrodes is formed so as to extend to the end of the gate trenchalong the formation direction of the gate trench while maintaining astate of being electrically separated by the intermediate insulatingfilm.

A lower-electrode contact that is connected only to the lower electrodeand an upper-electrode contact that is connected only to the upperelectrode are formed at the end of the gate trench. The lower-electrodecontact and the upper-electrode contact are formed so as to be exposedon the opening side of the gate trench. The lower-electrode contact andthe upper-electrode contact are connected together by means of anelectrode film or the like that is formed outside the gate trench. As aresult, the lower electrode and the upper electrode are electricallyconnected (short-circuited) together in a region outside the gatetrench.

However, in the thus formed arrangement, the lower electrode and theupper electrode are separated from each other by means of theintermediate insulating film in the gate trench. This makes itimpossible to transmit heat generated in the lower electrode directly tothe upper electrode and makes it impossible to dissipate the heatoutwardly from the gate trench. Additionally, a connection portionbetween the lower electrode and the upper electrode is apart from a heatgeneration source, and therefore it is impossible to efficientlydissipate the heat. Therefore, the inside of the gate trench is liableto be filled with the heat, and it is impossible to say that this isdesirable from the viewpoint of reliability. Therefore, in order toimprove the reliability of the trench gate structure and, consequently,to improve the reliability of the semiconductor device, it is necessaryto restrain a rise in temperature in the gate trench.

Additionally, in an arrangement in which each of the lower and upperelectrodes is drawn around to the end of the gate trench, a resistancevalue increases in proportion to the increase of the wiring length ofthe lower and upper electrodes in addition to the fact that thestructure of the device becomes complex. Additionally, the resistancevalues of the lower and upper electrodes are liable to increase inproportion to a rise in temperature in the gate trench. As a result,this also causes obstruction to the lowering of resistance.

On the other hand, according to the arrangement of the presentinvention, the gate contact is formed in the gate trench so as to passthrough the upper electrode and through the intermediate insulating filmand so as to reach the lower electrode. The gate contact electricallyconnects (short-circuits) the lower electrode and the upper electrodetogether in the gate trench. Additionally, the gate contact is formednear a heat generation source, and therefore it is possible to allow thegate contact to function as a heat dissipation material.

This makes it possible to dissipate heat generated in the lowerelectrode outwardly from the gate trench through the gate contact, andhence makes it possible to restrain a rise in temperature in the gatetrench. Additionally, when the semiconductor device of the presentinvention is employed as an in-vehicle power-based switching element, itis possible to realize an excellent dynamic clamp capacity by means ofthe restraint effect of a rise in temperature. Therefore, according tothe arrangement of the present invention, it is possible to provide asemiconductor device that has excellent reliability.

Additionally, according to the arrangement of the present invention, theelectric connection (short circuit) between the lower electrode and theupper electrode is achieved by the gate contact, and therefore, asdescribed above, the lower electrode and the upper electrode are notrequired to be drawn around to the end of the gate trench. This makes itpossible to avoid the structural complication of the semiconductordevice. Additionally, this makes it possible to prevent the increase ofthe resistance value caused by drawing around the lower electrode andthe upper electrode. Still additionally, it is possible to restrain arise in temperature in the gate trench, and therefore it is alsopossible to restrain the increase of the resistance values of the lowerand upper electrodes that is caused by a rise in temperature. As aresult, it is possible to lower the resistance of the semiconductordevice.

A semiconductor device that fulfills the same effects as theaforementioned effects is producible by performing asemiconductor-device manufacturing method including a step of forming agate trench in a semiconductor layer, a step of forming a gateinsulating film along an inner surface of the gate trench, a step offorming a lower electrode by burying a conductive material to a halfwayportion in a depth direction of the gate trench, a step of forming anintermediate insulating film by coating the lower electrode with aninsulating film, a step of forming an upper electrode by burying aconductive material so as to backfill the gate trench from above theintermediate insulating film, and a step of forming a gate contact thatelectrically connects the lower electrode and the upper electrodetogether by allowing the gate contact to pass through the upperelectrode and through the intermediate insulating film and to reach thelower electrode.

Preferably, the gate contact is formed along a longitudinal direction ofthe gate trench.

According to this arrangement, the gate contact is formed along the gatetrench, and therefore it is possible to effectively enlarge an area inwhich the gate contact functions as a heat dissipation material. As aresult, it is possible to effectively improve a heat dissipationcapability brought about by the gate contact.

The semiconductor device that fulfills the same effects as these effectsis producible by forming the gate contact along the longitudinaldirection of the gate trench in the manufacturing method of thesemiconductor device.

In the semiconductor device, the gate contact may have a bottom portionthat is contiguous to an upper end portion of the lower electrode andthat is contiguous to the intermediate insulating film. Additionally, inthe semiconductor device, the gate contact may have a bottom portioncontiguous to an upper end portion of the lower electrode and may have aside portion contiguous to the intermediate insulating film. It ispossible to excellently electrically connect (short-circuit) the upperelectrode and the lower electrode together by positioning the bottomportion of the gate contact at a depth lower than the intermediateinsulating film. In these arrangements, the upper electrode may have alower end portion that extends toward the lower electrode side and thatfaces the side portion of the lower electrode with the intermediateinsulating film therebetween.

Preferably, the semiconductor device includes a second conductivity typebody region formed at a surface portion of the semiconductor layer and afirst conductivity type region formed in the body region, in which thegate insulating film includes a thick film portion contiguous to thelower electrode and a thin film portion that is smaller in thicknessthan the thick film portion and that is interposed between the upperelectrode and the body region.

According to this arrangement, the lower electrode faces thesemiconductor layer with the thick film portion of the gate insulatingfilm therebetween, and therefore it is possible to reduce the capacityelement in the lower part of the gate electrode. Additionally, the upperelectrode faces the body region with the thin film portion of the gateinsulating film therebetween. This makes it possible to improve channelcontrollability. As a result, it is possible to effectively improve theswitching response speed of the semiconductor device.

Here, when a semiconductor layer having a first conductivity type layeris formed and when the first conductivity type region includes a sourceregion, it is possible to provide a semiconductor device having a VDMIS(Vertical Double Diffused Metal-Insulator-Semiconductor Field-EffectTransistor). On the other hand, when a semiconductor layer having asecond conductivity type layer is formed and when the first conductivitytype region includes an emitter region, it is possible to provide asemiconductor device having an IGBT (Insulated Gate Bipolar Transistor).Of course, a semiconductor layer having both the first conductivity typelayer and the second conductivity type layer may be formed, and asemiconductor device having both characteristics of the VDMIS and theIGBT may be manufactured.

The semiconductor device that fulfills the same effects as these effectsis producible by performing the semiconductor-device manufacturingmethod including a step of, prior to a step of forming the intermediateinsulating film, allowing the gate insulating film contiguous to thelower electrode to remain as a thick film portion by selectivelyremoving the gate insulating film to the halfway portion in the depthdirection of the gate trench, the step of forming the intermediateinsulating film including a step of forming the insulating film that hasa thickness smaller than the thick film portion along the inner surfaceof the gate trench from which the gate insulating film has been removedand forming a thin film portion serving as the gate insulating film, astep of forming a body region facing the upper electrode with the thinfilm portion of the gate insulating film between the body region and theupper electrode by implanting a second conductivity type impurity into asurface portion of the semiconductor layer, and a step of forming afirst conductivity type region by implanting a first conductivity typeimpurity into a surface portion of the semiconductor layer in the bodyregion.

Preferably, in the semiconductor device, the thin film portion of thegate insulating film has a thickness of 1/10 or less with respect to thethick film portion of the gate insulating film.

The semiconductor device may include a contact for use in the firstconductivity type region, the contact being formed so as to pass throughthe first conductivity type region and so as to reach the body region.

According to this arrangement, the contact for use in the firstconductivity type region also functions as a heat dissipation materialin the same way as the gate contact. Therefore, heat generated in thesemiconductor layer is dissipated outwardly from the semiconductor layerthrough the contact for use in the first conductivity type region. As aresult, the heat dissipation capability of the entire semiconductordevice is improved. Additionally, it is possible to form the contact foruse in the first conductivity type region even closer to the gateelectrode than in a case in which the contact for use in the firstconductivity type region is formed on the semiconductor layer. Thismakes it possible to further improve channel controllability.

The semiconductor device that fulfills the same effects as these effectsis producible by performing the semiconductor-device manufacturingmethod including a step of forming a contact for use in the firstconductivity type region, the contact passing through the firstconductivity type region and reaching the body region.

In the semiconductor device, the contact for use in the firstconductivity type region may have a bottom portion at a positionshallower than the bottom portion of the gate contact. Preferably, inthe semiconductor device, the contact for use in the first conductivitytype region is formed along the longitudinal direction of the gatetrench. According to this arrangement, the contact for use in the firstconductivity type region is formed along the gate trench, and thereforeit is possible to further enlarge an area in which the contact for usein the first conductivity type region functions as a heat dissipationmaterial. As a result, it is possible to further improve a heatdissipation capability brought about by the contact for use in the firstconductivity type region.

Preferably, in the semiconductor device, the contact for use in thefirst conductivity type region includes tungsten. According to thisarrangement, the contact for use in the first conductivity type regionthat has an excellent heat dissipation capability is realized bytungsten that has excellent thermal conductivity.

The semiconductor device that fulfills the same effects as these effectsis producible by forming the contact for use in the first conductivitytype region that includes tungsten in the semiconductor-devicemanufacturing method.

Preferably, the semiconductor device includes an interlayer insulatingfilm formed on the semiconductor layer, in which the gate contact isformed so as to pass through the interlayer insulating film. Accordingto this arrangement, an area in which the gate contact functions as aheat dissipation material is further enlarged. As a result, the heatdissipation capability of the gate contact is even further improved.

The semiconductor device that fulfills the same effects as these effectsis producible by performing the semiconductor-device manufacturingmethod including a step of forming an interlayer insulating film withwhich the semiconductor layer is covered after the step of forming theupper electrode and prior to the step of forming the gate contact, inwhich the gate contact is formed so as to pass through the interlayerinsulating film, the upper electrode, and the intermediate insulatingfilm in this order and so as to reach the lower electrode.

Preferably, in the semiconductor device, the gate contact includestungsten. According to this arrangement, the gate contact that has anexcellent heat dissipation capability is realized by tungsten that hasexcellent thermal conductivity.

The semiconductor device that fulfills the same effects as these effectsis producible by performing the semiconductor-device manufacturingmethod in which the gate contact that includes tungsten is formed.

In the semiconductor device, the semiconductor layer may include anelement region electrically separated by a DTI (Deep Trench Isolation)structure, and the DTI structure may include a DTI insulating filmformed along an inner surface of a DTI trench formed in thesemiconductor layer, a DTI electrode that is buried in the DTI trenchthrough the DTI insulating film and that has a lower DTI electrode andan upper DTI electrode that are separated upwardly and downwardly fromeach other with the DTI intermediate insulating film between the lowerDTI electrode and the upper DTI electrode, and a DTI contact that isformed in the DTI trench so as to pass through the upper DTI electrodeand through the DTI intermediate insulating film and so as to reach thelower DTI electrode and that electrically connects the lower DTIelectrode and the upper DTI electrode together.

According to this arrangement, the DTI structure has a split structurethat includes a lower DTI electrode and an upper DTI electrode that areseparated upwardly and downwardly from each other with an intermediateDTI insulating film therebetween. The element region is electricallyseparated from other regions by means of the DTI structure.Additionally, according to the DTI structure, the DTI contact alsofunctions as a heat dissipation material in the same way as the gatecontact. Therefore, heat generated in the element region or in thesemiconductor layer is dissipated outwardly from the semiconductor layerby means of the DTI structure. Moreover, it is possible to produce thisDTI structure through the same process as the trench gate structure (thesplit gate structure). Therefore, the number of manufacturing stepsnever increases only for forming the DTI structure. Preferably, a groundpotential is applied to the DTI contact.

The element region may include a CMIS(Complementary MIS) region, theCMIS region having a first conductivity type MISFET(Metal-Insulator-Semiconductor Field-Effect Transistor) and a secondconductivity type MISFET.

According to this arrangement, it is possible to provide a semiconductordevice having an IPM (Intelligent Power Module) structure in which theCMIS region serving as a control portion and the VDMIS region serving asa power portion are formed integrally with each other.

Preferred embodiments of the present invention will be hereinafterdescribed in detail with reference to the accompanying drawings.

First Preferred Embodiment

FIG. 1 is a schematic plan view of a semiconductor device 1 according toa first preferred embodiment of the present invention.

The semiconductor device 1 is a small semiconductor chip formed in aquadrangular shape when viewed planarly, and includes a VDMIS region 2that has a VDMIS (Vertical Double Diffused Metal-Insulator-SemiconductorField-Effect Transistor), a CMIS region 3 that has a CMIS (ComplementaryMIS), and a passive element region 4 that has passive elements, such asa capacitor and a resistor. The VDMIS region 2 is formed as a powerportion. On the other hand, the CMIS region 3 is formed as a controlportion. As a result, the semiconductor device 1 has an IPM (IntelligentPower Module) structure.

A source pad 6 to which, for example, a bonding wire is connected isselectively disposed on an uppermost layer of the VDMIS region 2 (seethe broken line portion of FIG. 1). The present preferred embodimentshows an example in which the source pad is disposed at an end of theVDMIS region 2.

The CMIS region 3 and the passive element region 4 are each formed apartfrom the VDMIS region 2, and are each surrounded by a DTI (Deep TrenchIsolation) structure 5 having a square annular shape when viewedplanarly (see the cross hatching portion). The CMIS region 3 and thepassive element region 4 are each separated electrically from the VDMISregion 2 by means of the DTI structure 5.

Hereinafter, an arrangement of the VDMIS region 2 will be firstdescribed with reference to FIG. 2 to FIG. 4, and then an arrangement ofthe CMIS region 3 will be described with reference to FIG. 5. Adescription of an arrangement of the passive element region 4 isomitted.

<VDMIS Region 2>

FIG. 2 is a perspective cross-sectional view of a region D surrounded bythe broken line of the VDMIS region 2 shown in FIG. 1. FIG. 3 is across-sectional view taken along line shown in FIG. 2. In FIG. 2, astructure of a semiconductor layer 10 is shown, in which an arrangementformed on the semiconductor layer 10 is selectively excluded.

The semiconductor device 1 includes the semiconductor layer 10 that isone example of the semiconductor layer of the present invention. Thesemiconductor layer 10 includes an n⁺ type semiconductor substrate 11and an n⁻ type epitaxial layer 12 formed on the semiconductor substrate11. The semiconductor substrate 11 has an impurity concentration of, forexample, 1.0×10¹⁸ cm⁻³ to 1.0×10²⁰ cm⁻³ (in the present preferredembodiment, 2.0×10¹⁹ cm⁻³). The epitaxial layer 12 has an impurityconcentration of, for example, 1.0×10¹⁵ cm⁻³ to 1.0×10¹⁷ cm⁻³ (in thepresent preferred embodiment, 1.0×10¹⁶ cm⁻³). The n type impurities are,for example, N (nitrogen), As (arsenic), P (phosphorus), or the like(hereinafter, the same applies).

A plurality of unit cells 13 forming a VDMIS are formed in the epitaxiallayer 12. The present preferred embodiment shows an example in which theunit cells 13 are formed in a stripe manner Hereinafter, an arrangementof the unit cells 13 will be specifically described.

A plurality of gate trenches 14 spaced out, which form a part of theunit cell 13, are formed in the epitaxial layer 12 in a stripe manner.The width of the gate trench 14 is, for example, 0.5 μm to 1.0 μm (inthe present preferred embodiment, 0.6 μm). The depth of the gate trench14 is, for example, 4.0 μm to 5.0 μm (in the present preferredembodiment, 4.2 μm). The side portion of each gate trench 14 may beformed perpendicularly to the surface of the epitaxial layer 12.Additionally, the edge portion at which the side portion and the bottomportion of each gate trench 14 intersect with each other may be formedso as to be curved outwardly from each gate trench 14.

A p type body region 15, an n type drift region 16, an n type sourceregion 17, and a p type contact region 18, each of which forms a part ofthe unit cell 13, are formed between mutually adjoining gate trenches14. The n type source region 17 is one example of a first conductivitytype region of the present invention.

The p type body region 15 is formed along the stripe direction of thegate trench 14. The p type body region 15 is formed, for example, 1.0 μmto 1.5 μm deep from the surface of the epitaxial layer 12. The p typebody region 15 is exposed to the side portion of each gate trench 14,and forms a part of the side portion of the gate trench 14. The p typebody region 15 has an impurity concentration of, for example, 1.0×10¹⁶cm⁻³ to 1.0×10¹⁸ cm⁻³ (in the present preferred embodiment, 3.0×10¹⁷cm⁻³). The p type impurities are, for example, B (boron), Al (aluminum),or the like (hereinafter, the same applies).

The n type drift region 16 is formed under the p type body region 15along the stripe direction of the gate trench 14. The n type driftregion 16 is formed at a depth of a halfway portion in the depthdirection of each gate trench 14 so as to come into contact with thebottom of the p type body region 15. The n type drift region 16 isexposed to the side portion of each gate trench 14, and forms a part ofthe side portion of the gate trench 14. The n type drift region 16 mayhave an impurity concentration higher than the epitaxial layer 12.

As shown in FIG. 2 and FIG. 3, the n type source region 17 and the ptype contact region 18 are formed more shallowly than the p type bodyregion 15, and are exposed from the surface of the epitaxial layer 12.The n type source region 17 is formed along the stripe direction of eachgate trench 14 so as to be exposed from both side portions of each gatetrench 14 (i.e., from both side portions in the direction perpendicularto the stripe direction). The n type source region 17 forms a part ofthe side portion of the gate trench 14. The n type source region 17 mayhave an impurity concentration higher than the epitaxial layer 12.

On the other hand, the p type contact region 18 is selectively formed soas to lie in a halfway portion in the stripe direction of the n typesource region 17, and is exposed from the side portion of the gatetrench 14. The p type contact region 18 may have an impurityconcentration higher than the p type body region 15. The p type contactregion 18 forms a part of the side portion of the gate trench 14.

A gate electrode 25 is embedded in the gate trench 14 with a gateinsulating film 20 therebetween. As a result, a trench gate structure 19is formed. The gate electrode 25 has a split gate structure thatincludes a lower electrode layer 26 and an upper electrode layer 30 thathave been separated upwardly and downwardly between which anintermediate insulating film 24 is sandwiched. The lower electrode layer26 and the upper electrode layer 30 may be polysilicon layers each ofwhich is doped with, for example, p type impurities.

An arrangement of the trench gate structure 19 will be hereinafterdescribed in more detail with reference to FIG. 4. FIG. 4 is an enlargedcross-sectional view around the trench gate structure 19 shown in FIG.3.

As shown in FIG. 4, the gate insulating film 20 includes a thick filmportion 21 contiguous to the lower electrode layer 26 and a first thinfilm portion 22 that has a thickness smaller than the thick film portion21 and that is interposed between the upper electrode layer 30 and the ptype body region 15. The gate insulating film 20 additionally includes asecond thin film portion 23 that has a thickness smaller than the thickfilm portion 21 and that covers the upper electrode layer 30.Preferably, the first thin film portion 22 of the gate insulating film20 has a thickness equal to or lower than 1/10 of the thickness of thethick film portion 21. The thick film portion 21 of the gate insulatingfilm 20 may have a thickness of, for example, 3000 Å to 5000 Å. Thefirst thin film portion 22 of the gate insulating film 20 may have athickness of, for example, 250 Å to 500 Å. The gate insulating film 20may be, for example, a silicon oxide film (SiO₂).

The lower electrode layer 26 of the gate electrode 25 is formed so as tobackfill the gate trench 14 to the halfway portion in the depthdirection of the gate trench 14 through the thick film portion 21 of thegate insulating film 20. The lower electrode layer 26 has a lower endportion 27 facing the epitaxial layer 12 (an end portion on the bottomside of the gate trench 14) with the thick film portion 21 of the gateinsulating film 20 therebetween. The lower electrode layer 26additionally has an upper end portion 28 facing the n type drift region16 (an end portion on the opening side of the gate trench 14) with thethick film portion 21 of the gate insulating film 20 therebetween. Theupper end portion 28 of the lower electrode layer 26 includes a convexportion 29 formed so as to protrude toward the opening side of the gatetrench 14.

The present preferred embodiment shows an example in which the convexportion 29 of the lower electrode layer 26 has a width W2 smaller than awidth W1 of the other parts of the lower electrode layer 26 with respectto the direction perpendicular to the depth direction of the gate trench14. However, an arrangement may be formed so that the upper end portion28 is regarded as not having the convex portion 29 by making the convexportion 29 substantially equal in width to the other parts of the lowerelectrode layer 26 (width W1 width W2). The intermediate insulating film24 is formed so as to cover this convex portion 29.

The intermediate insulating film 24 is formed along the convex portion29 of the lower electrode layer 26. The intermediate insulating film 24is formed at a boundary between the thick film portion 21 and the firstthin film portion 22 so as to be integrally continuous with the thickfilm portion 21 and with the first thin film portion 22 of the gateinsulating film 20. In other words, the intermediate insulating film 24forms a part of the gate insulating film 20. The intermediate insulatingfilm 24 is smaller in thickness than the thick film portion 21 of thegate insulating film 20, and is greater in thickness than the first thinfilm portion 22 of the gate insulating film 20. The intermediateinsulating film 24 may have a thickness greater than 500 Å, e.g., mayhave a thickness of 600 Å. The intermediate insulating film 24 may be,for example, a silicon oxide film (SiO₂).

The upper electrode layer 30 of the gate electrode 25 is formed on theintermediate insulating film 24 so as to backfill the gate trench 14through the first thin film portion 22 of the gate insulating film 20.The upper electrode layer 30 faces the p type body region 15 with thefirst thin film portion 22 of the gate insulating film 20 therebetween.More specifically, the upper electrode layer 30 has a lower end portion31 (an end portion on the bottom side of the gate trench 14) thatextends toward the lower electrode layer 26 and that crosses a boundarybetween the p type body region 15 and the n type drift region 16. Theupper electrode layer 30 additionally has an upper end portion 32 (anend portion on the opening side of the gate trench 14) that extendstoward the opening side of the gate trench 14 and that crosses aboundary between the p type body region 15 and the n type source region17 and a boundary between the p type body region 15 and the p typecontact region 18 (see FIG. 2 also).

The lower end portion 31 of the upper electrode layer 30 is positionedbetween the bottom of the p type body region 15 and the bottom of the ntype drift region 16. The lower end portion 31 of the upper electrodelayer 30 faces a side portion of the lower electrode layer 26 with theintermediate insulating film 24 therebetween. More specifically, thelower end portion 31 of the upper electrode layer 30 faces a sideportion of the convex portion 29 of the lower electrode layer 26 withthe intermediate insulating film 24 therebetween. The upper electrodelayer 30 is formed so as to overlap with the upper end portion 28 of thelower electrode layer 26.

On the other hand, the upper end portion 32 of the upper electrode layer30 is positioned between the opening of the gate trench 14 and thebottom of the n type source region 17 (the p type contact region 18). Asa result, the upper electrode layer 30 has a side portion 33 facing thep type body region 15 with the first thin film portion 22 of the gateinsulating film 20 therebetween from the side of the upper end portion32 to the side of the lower end portion 31.

A region faced by the upper electrode layer 30 in the p type body region15 with the first thin film portion 22 of the gate insulating film 20therebetween is a channel region 34 of the VDMIS. The formation of achannel in the channel region 34 is controlled by the upper electrodelayer 30 of the gate electrode 25.

The second thin film portion 23 of the gate insulating film 20 is formedso as to backfill the gate trench 14 from above the upper electrodelayer 30 in such a way as to cover the upper end portion 32 of the upperelectrode layer 30. The second thin film portion 23 of the gateinsulating film 20 is contiguous to the n type source region 17 and thep type contact region 18 that are exposed from the side portion of thegate trench 14 (see FIG. 2 also). For example, the second thin filmportion 23 of the gate insulating film 20 may have the same thickness(250 Å to 500 Å) as the first thin film portion 22. Additionally, forexample, the second thin film portion 23 of the gate insulating film 20may have the same thickness as the intermediate insulating film 24(greater than 500 Å, e.g., equal to 600 Å). The second thin film portion23 is formed so as to be integrally continuous with the first thin filmportion 22 and with a surface insulating film 40 formed on the epitaxiallayer 12.

The surface insulating film 40 may be, for example, a silicon oxide film(SiO₂). The surface insulating film 40 may have the same thickness asthe first thin film portion 22 or the second thin film portion 23 of thegate insulating film 20.

In the VDMIS region 2, the gate electrode 25 is buried in the gatetrench 14 in this way, and, as a result, the trench gate structure 19 isformed. The unit cell 13 forming the VDMIS is defined by a regionsandwiched between the center lines (boundaries) between mutuallyadjoining trench gate structures 19. In other words, one unit cell 13includes one trench gate structure 19.

As shown in FIG. 3 and FIG. 4, an interlayer insulating film 42 isformed on the epitaxial layer 12 (the surface insulating film 40) so asto cover the trench gate structure 19. The interlayer insulating film 42may include, for example, silicon oxide (SiO₂), silicon nitride (SiN),and the like. The interlayer insulating film 42 has a thickness of, forexample, 2000 Å to 5000 Å. The interlayer insulating film 42 has a gatecontact 43 electrically connected to the trench gate structure 19.

The gate contact 43 is formed along the stripe direction of the gatetrench 14. The gate contact 43 is formed so as to pass through theinterlayer insulating film 42, the second thin film portion 23 of thegate insulating film 20, the upper electrode layer 30, and theintermediate insulating film 24 in this order and so as to reach thelower electrode layer 26. The gate contact 43 has a side portioncontiguous to the interlayer insulating film 42, to the second thin filmportion 23 of the gate insulating film 20, and to the upper electrodelayer 30, and has a bottom portion contiguous to the upper end portion28 (the convex portion 29) of the lower electrode layer 26 and to theintermediate insulating film 24. The lower electrode layer 26 and theupper electrode layer 30 that are formed in the gate trench 14 areelectrically connected (short-circuited) together by means of the gatecontact 43.

In the present preferred embodiment, let it be supposed that the term“to pass through” denotes that a component passes through ato-be-penetrated object and then exits from the object to an oppositeside, and, in addition, denotes that a component reaches anothercomponent through a portion formed by removing a part of ato-be-penetrated object (hereinafter, the same applies). In other words,the gate contact 43 may be regarded as being formed so as to reach thelower electrode layer 26 through a portion formed by removing a part ofthe objects consisting of the interlayer insulating film 42, the secondthin film portion 23 of the gate insulating film 20, the upper electrodelayer 30, and the intermediate insulating film 24.

As shown in FIG. 4, the gate contact 43 has a trench contact structurethat includes a gate contact trench 44 and a conductor layer 45 buriedin the gate contact trench 44.

The gate contact trench 44 is formed by digging down the interlayerinsulating film 42, the second thin film portion 23 of the gateinsulating film 20, the upper electrode layer 30, and the intermediateinsulating film 24 in this order so as to reach the lower electrodelayer 26. The gate contact trench 44 has a side portion to which theinterlayer insulating film 42, the second thin film portion 23 of thegate insulating film 20, and the upper electrode layer 30 are exposed,and has a bottom portion to which the intermediate insulating film 24and the lower electrode layer 26 (the convex portion 29) are exposed.

The conductor layer 45 of the gate contact 43 has a layered structure inwhich a plurality of conductive materials are stacked together. Morespecifically, the gate contact 43 has a first conductor layer 46 formedalong the inner surface of the gate contact trench 44 and a secondconductor layer 47 formed along the surface of the first conductor layer46.

The first conductor layer 46 has its front surface and its back surface(a surface on the side of the gate contact trench 44) that are formedalong the inner surface of the gate contact trench 44. The secondconductor layer 47 has a thickness greater than the first conductorlayer 46, and is formed so as to backfill the gate contact trench 44from above the first conductor layer 46. Preferably, the percentage ofthe second conductor layer 47 with respect to the gate contact trench 44is greater than that of the first conductor layer 46 with respect to thegate contact trench 44. The conductive material of the first conductorlayer 46 may be, for example, titanium (Ti), titanium nitride (TiN), orthe like. On the other hand, the conductive material of the secondconductor layer 47 may be, for example, tungsten (W).

The interlayer insulating film 42 additionally has a source contact 48formed so as to pass through the interlayer insulating film 42 andthrough the surface insulating film 40 and so as to be electricallyconnected to the n type source region 17. The source contact 48 isformed between the gate trenches 14 along the stripe direction of thegate trench 14. The source contact 48 is formed so as to cross theborderline between mutually adjoining unit cells 13.

As shown in FIG. 4, the source contact 48 has a trench contact structurethat includes a source contact trench 49 and a conductor layer 50 buriedin the source contact trench 49.

The source contact trench 49 is formed by digging down the interlayerinsulating film 42, the surface insulating film 40, and the epitaxiallayer 12 (the n type source region 17 and the p type contact region 18)in this order. The source contact trench 49 has a bottom portion thatreaches the p type body region 15. A side portion of the source contacttrench 49 may be formed perpendicularly to the surface of the epitaxiallayer 12. An edge portion at which the side portion and the bottomportion of the source contact trench 49 intersect with each other may beformed so as to be curved outwardly from the source contact trench 49. Ap type extra contact region 51 is selectively formed at a part along theside portion and the bottom portion of the source contact trench 49 inthe p type body region 15.

The p type extra contact region 51 is formed along the side portion andthe bottom portion of the source contact trench 49 from the bottomportion of the n type source region 17 and from the bottom portion ofthe p type contact region 18 (see FIG. 2). The n type source region 17,the p type contact region 18 (see FIG. 2), and the p type extra contactregion 51 are exposed from the side portion and the bottom portion ofthe source contact trench 49. In other words, the n type source region17, the p type contact region 18 (see FIG. 2), and the p type extracontact region 51 form a part of the side portion of the source contacttrench 49, and form the bottom portion of the source contact trench 49.The side portion of the source contact trench 49 faces the side portionof the gate trench 14 (the trench gate structure 19) with the p typeextra contact region 51 and the p type body region 15 therebetween.

The conductor layer 50 of the source contact 48 has a layered structureconsisting of the first conductor layer 46 and the second conductorlayer 47 in the same way as the gate contact 43. The conductor layer 50buried in the source contact trench 49 forms an ohmic contact betweenthe p type extra contact region 51 and the conductor layer 50.

As shown in FIG. 3, a USG film 55 made of USG (Undoped Silica Glass) isformed on the interlayer insulating film 42. The USG film 55 may have athickness of, for example, 2000 Å to 5000 Å. The USG film 55 has asource plug 56 formed so as to pass through the USG film 55 and so as tobe connected to the source contact 48.

The source plug 56 includes a plug trench 57 that is for use in plugsand that is formed in the USG film 55 and a conductor layer 58 buried inthe plug trench 57. The plug trench 57 may be formed along the sourcecontact 48 in a stripe manner. The conductor layer 58 of the source plug56 has a layered structure consisting of the first conductor layer 46and the second conductor layer 47 in the same way as the gate contact43. A source electrode film 59 is formed on the USG film 55 so as tocover the source plug 56.

The source electrode film 59 is electrically connected to the sourceplug 56 formed in the USG film 55. Preferably, the source electrode film59 is formed so as to overlap with at least one trench gate structure 19(one unit cell 13). The present preferred embodiment shows an example inwhich the source electrode film 59 is formed so as to cover the whole ofthe VDMIS region 2, i.e., so as to cover a region in which all unitcells 13 are formed. Preferably, the source electrode film 59 is madeof, for example, Al (aluminum), or Cu (copper), or an alloy (AlCu) ofthese elements (in the present preferred embodiment, AlCu). The sourceelectrode film 59 may have a thickness of, for example, 5 μm to 10 μm. Asecond interlayer insulating film and a second USG film may be formed onthe source electrode film 59 in this order.

The source pad 6 (see FIG. 1) is electrically connected to the sourceelectrode film 59. A ground potential (a reference voltage) is appliedto the source electrode film 59 through the source pad 6. Electric powerinput to the source electrode film 59 is transmitted to the sourcecontact 48 through the source plug 56. On the other hand, a gateelectrode film, a gate electrode pad, and the like (not shown) each ofwhich transmits a gate voltage applied in other regions to the gatecontact 43 may be electrically connected to the gate contact 43.Electric power input to the gate electrode pad and the like istransmitted to the trench gate structure 19 through the gate contact 43.A drain electrode 60 serving as a back-surface electrode is formed onthe back surface of the semiconductor layer 10 (the semiconductorsubstrate 11). A VDMIS is thus arranged in the VDMIS region 2.

As described above, the trench gate structure 19 in which the gateelectrode 25 is buried in the gate trench 14 is formed in the VDMISregion 2. Additionally, the gate electrode 25 has a split gate structurethat includes the lower electrode layer 26 and the upper electrode layer30 that have been separated upwardly and downwardly from each other bymeans of the intermediate insulating film 24.

A method for drawing around and connecting each of the lower and upperelectrode layers 26 and 30 to the end of the gate trench 14 can bementioned as an example of a connection method of the lower electrodelayer 26 and the upper electrode layer 30 in the split gate structure.In this case, for example, each of the lower and upper electrode layers26 and 30 is formed so as to extend to the end of the gate trench 14along the stripe direction while maintaining a state of beingelectrically separated by means of the intermediate insulating film 24.

A lower-electrode-layer contact that is connected only to the lowerelectrode layer 26 and an upper-electrode-layer contact that isconnected only to the upper electrode layer 30 are formed at the end ofthe gate trench 14. The lower-electrode-layer contact and theupper-electrode-layer contact are formed so as to be exposed on theopening side of the gate trench 14. The lower-electrode-layer contactand the upper-electrode-layer contact are connected together by means ofan electrode film or the like that is formed outside the gate trench 14.As a result, the lower electrode layer 26 and the upper electrode layer30 are electrically connected (short-circuited) together in a regionoutside the gate trench 14.

However, in the thus formed arrangement, the lower electrode layer 26and the upper electrode layer 30 are separated from each other by meansof the intermediate insulating film 24 in the gate trench 14. This makesit impossible to transmit heat generated in the lower electrode layer 26directly to the upper electrode layer 30 and to dissipate the heatoutwardly from the gate trench 14. Additionally, a connection portionbetween the lower electrode layer 26 and the upper electrode layer 30 isapart from a heat generation source, and therefore it is impossible toefficiently dissipate the heat. Therefore, the inside of the gate trench14 is liable to be filled with the heat, and it is impossible to saythat this is desirable from the viewpoint of reliability. Therefore, inorder to improve the reliability of the trench gate structure and,consequently, to improve the reliability of the semiconductor device, itis necessary to restrain a rise in temperature in the gate trench 14.

Additionally, in an arrangement in which each of the lower and upperelectrode layers 26 and 30 is drawn around to the end of the gate trench14, a resistance value increases in proportion to the increase of thewiring length of the lower and upper electrode layers 26 and 30 inaddition to the fact that the structure of the device becomes complex.Additionally, the resistance values of the lower and upper electrodelayers 26 and 30 are liable to increase in proportion to a rise intemperature in the gate trench 14. As a result, this also causesobstruction to the lowering of resistance.

On the other hand, according to the present preferred embodiment, thegate contact 43 is formed in the gate trench 14 so as to pass throughthe upper electrode layer 30 and through the intermediate insulatingfilm 24 and so as to reach the lower electrode layer 26. The gatecontact 43 electrically connects (short-circuits) the lower electrodelayer 26 and the upper electrode layer 30 together in the gate trench14. Additionally, the gate contact 43 includes tungsten excellent inthermal conductivity, and is formed near a heat generation source. Stilladditionally, this gate contact 43 is formed so as to pass through theinterlayer insulating film 42 along the stripe direction of the gatetrench 14.

This makes it possible to allow the gate contact 43 to function as aheat dissipation material in a wide area, and hence makes it possible toeffectively dissipate heat generated in the lower electrode layer 26through the gate contact 43. As a result, it is possible to effectivelyrestrain a rise in temperature in the gate trench 14. Additionally, whenthe semiconductor device 1 is employed as an in-vehicle power-basedswitching element, it is possible to realize an excellent dynamic clampcapacity by the restraint effect of a rise in temperature. Therefore, itis possible to provide a semiconductor device 1 that has excellentreliability.

Additionally, according to the present preferred embodiment, theelectric connection between the lower electrode layer 26 and the upperelectrode layer 30 is achieved by the gate contact 43 in the gate trench14, and therefore, as described above, the lower electrode layer 26 andthe upper electrode layer 30 are not required to be drawn around to theoutside of the gate trench 14. This makes it possible to avoid thestructural complication of the semiconductor device 1. Additionally,this makes it possible to prevent the increase of the resistance valuecaused by drawing around the lower electrode layer 26 and the upperelectrode layer 30. Still additionally, it is possible to restrain arise in temperature in the gate trench 14, and therefore it is alsopossible to restrain the increase of the resistance values of the lowerand upper electrode layers 26 and 30 that is caused by a rise intemperature. As a result, it is possible to lower the resistance of thesemiconductor device 1.

Additionally, according to the present preferred embodiment, the sourcecontact 48 is formed so as to pass through the surface insulating film40 and through the epitaxial layer 12 and so as to be electricallyconnected to the n type source region 17. The source contact 48 isformed with the same arrangement as the gate contact 43. In other words,the source contact 48 functions as a heat dissipation material.Moreover, the source electrode film 59 with which at least one trenchgate structure 19 (one unit cell 13) is covered is connected to thesource contact 48. This makes it possible to effectively dissipate heatgenerated in the epitaxial layer 12 and the like outwardly from theepitaxial layer 12 through the source contact 48 and through the sourceelectrode film 59. As a result, it is possible to effectively improvethe heat dissipation capability of the entire semiconductor device 1.

Additionally, according to the present preferred embodiment, the sideportion of the source contact 48 and the side portion of the gate trench14 face each other with the p type body region 15 therebetween.Therefore, the controllability of the channel (the channel region 34) isfurther improved than in a case in which the source contact 48 is formedon the epitaxial layer 12 so as to pass only through the interlayerinsulating film 42 and the surface insulating film 40 and so as to becontiguous to the n type source region 17.

Additionally, according to the present preferred embodiment, the gateinsulating film 20 includes the thick film portion 21 contiguous to thelower electrode layer 26 and the first thin film portion 22 contiguousto the upper electrode layer 30. Therefore, the lower electrode layer 26faces the epitaxial layer 12 with the thick film portion 21 of the gateinsulating film 20 therebetween, and therefore it is possible to reducethe capacity element in the lower part of the trench gate structure 19.Additionally, the upper electrode layer 30 faces the p type body region15 with the first thin film portion 22 of the gate insulating film 20therebetween. This makes it possible to improve the controllability ofthe channel (the channel region 34). As a result, it is possible toeffectively improve the switching response speed of the VDMIS.

<CMIS Region 3>

FIG. 5 is a schematic cross-sectional view to describe the CMIS region 3of FIG. 1, taken along line V-V shown in FIG. 1. In FIG. 5, the samereference sign as in FIG. 1 to FIG. 4 is given to a componentcorresponding to each component of FIG. 1 to FIG. 4 mentioned above, anda description of this component is omitted.

As shown in FIG. 1 and FIG. 5, the CMIS region 3 includes an n-MISregion 61 and a p-MIS region 62 that are electrically separated fromeach other by means of the DTI structure 5. An n type MISFET(Metal-Insulator-Semiconductor Field-Effect Transistor) is formed in then-MIS region 61, whereas a p type MISFET is formed in the p-MIS region62.

Hereinafter, an arrangement of the DTI structure 5 will be firstdescribed, and then an arrangement of the n-MIS region 61 and anarrangement of the p-MIS region 62 will be described.

<DTI Structure 5>

As shown in FIG. 5, the DTI structure 5 includes a DTI trench 63 that isfor use in DTIs and that is formed in the epitaxial layer 12. The DTItrench 63 has the same depth as the aforementioned gate trench 14. Onthe other hand, the width of the DTI trench 63 is, for example, 1 μm to2 μm (in the present preferred embodiment, 1.8 μm), and is formed so asto be greater than the width (0.5 μm to 1.0 μm) of the gate trench 14. ADTI electrode 68 that is for use in DTIs is embedded in the DTI trench63 through a DTI insulating film 64 that is for use in DTIs. The DTIelectrode 68 has a split structure that includes a lower DTI electrodelayer 69 and an upper DTI electrode layer 70 that are separated upwardlyand downwardly from each other with an intermediate DTI insulating film67 therebetween.

The DTI insulating film 64 includes a first part 65 that is formed alongthe inner surface of the DTI trench 63 and that is contiguous to thelower DTI electrode layer 69 and to the upper DTI electrode layer 70 anda second part 66 with which an area on the upper DTI electrode layer 70is covered. The first part 65 of the DTI insulating film 64 may have,for example, the same thickness (3000 Å to 5000 Å) as the thick filmportion 21 of the gate insulating film 20.

The lower DTI electrode layer 69 of the DTI electrode 68 is formed so asto backfill the DTI trench 63 to the halfway portion in the depthdirection of the DTI trench 63 through the first part 65 of the DTIinsulating film 64. The intermediate DTI insulating film 67 is formed soas to cover the lower DTI electrode layer 69.

The intermediate DTI insulating film 67 is formed so as to be integrallycontinuous with the first part 65. The intermediate DTI insulating film67 may have a thickness smaller than the first part 65. The intermediateDTI insulating film 67 may have the same thickness as the intermediateinsulating film 24 (which is equal to or greater than 500 Å, e.g., whichis 600 Å).

The upper DTI electrode layer 70 of the DTI electrode 68 is formed so asto backfill the DTI trench 63 from above the intermediate DTI insulatingfilm 67 through the first part 65 of the DTI insulating film 64.

The second part 66 of the DTI insulating film 64 is formed so as tobackfill the DTI trench 63 from above the upper DTI electrode layer 70in such a way as to cover the upper end portion of the upper DTIelectrode layer 70. The second part 66 is formed so as to be integrallycontinuous with the surface insulating film 40 formed on the epitaxiallayer 12. The second part 66 may have, for example, the same thicknessas the second thin film portion 23 of the gate insulating film 20.

A DTI contact 73 that is electrically connected to the DTI electrode 68is formed on the interlayer insulating film 42. The DTI contact 73 isformed along the DTI trench 63. The DTI contact 73 may be formed in asquare annular shape along the DTI trench 63 when viewed planarly (seeFIG. 1 also), or may be formed by a plurality of contacts that arespaced out along the square annular shape when viewed planarly.

The DTI contact 73 is formed by passing through the interlayerinsulating film 42, the second part 66 of the DTI insulating film 64,the upper DTI electrode layer 70, and the intermediate DTI insulatingfilm 67 in this order so as to reach the lower DTI electrode layer 69.The DTI contact 73 has a side portion contiguous to the intermediate DTIinsulating film 67 and to the upper DTI electrode layer 70 and a bottomportion contiguous to the lower DTI electrode layer 69. The lower DTIelectrode layer 69 and the upper DTI electrode layer 70 that are formedin the DTI trench 63 are electrically connected (short-circuited)together by means of the DTI contact 73.

The DTI contact 73 includes a DTI contact trench 74 and a conductorlayer 75 buried in the DTI contact trench 74. The DTI contact trench 74is formed by digging down the interlayer insulating film 42, the secondpart 66 of the DTI insulating film 64, the upper DTI electrode layer 70,and the intermediate DTI insulating film 67 in this order so as to reachthe lower DTI electrode layer 69. The DTI contact trench 74 has a sideportion to which the interlayer insulating film 42, the second part 66of the DTI insulating film 64, the upper DTI electrode layer 70, and theintermediate DTI insulating film 67 of the DTI insulating film 64 areexposed and a bottom portion to which the lower DTI electrode layer 69is exposed.

The conductor layer 75 of the DTI contact 73 has a layered structureconsisting of the first conductor layer 46 and the second conductorlayer 47 in the same way as the gate contact 43 mentioned above. A DTIplug 76 that passes through the USG film 55 and that is connected to theDTI contact 73 is additionally formed in the USG film 55 in the CMISregion 3.

The DTI plug 76 includes a DTI plug trench 77 formed in the USG film 55and a conductor layer 78 buried in the DTI plug trench 77. The DTI plugtrench 77 may be formed along the DTI contact 73. The conductor layer 78of the DTI plug 76 has a layered structure consisting of the firstconductor layer 46 and the second conductor layer 47 in the same way asthe gate contact 43. For example, the aforementioned source electrodefilm 59 or another source electrode film is connected to the DTI plug76, and a ground potential is applied thereto.

As described above, the CMIS region 3 and the VDMIS region 2 areelectrically separated from each other by means of the DTI structure 5.Additionally, the n-MIS region 61 and the p-MIS region 62 are furtherpartitioned from each other by means of the DTI structure 5 in the CMISregion 3, so that an electric separation between the n-MIS region 61 andthe p-MIS region 62 is achieved.

According to the DTI structure 5, it is possible not only toelectrically separate a plurality of element regions (the VDMIS region 2and the CMIS region 3) from each other but also to dissipate heatgenerated in the CMIS region 3, the epitaxial layer 12, and the likeoutwardly from the epitaxial layer 12 by means of the DTI structure 5(the DTI contact 73). Moreover, it is possible to produce the DTIstructure 5 having the thus formed split structure (the DTI electrode68) according to the same process as the trench gate structure 19 havingthe aforementioned split gate structure (the gate electrode 25). Thismakes it possible to further improve the heat dissipation capability ofthe semiconductor device 1. Additionally, the number of manufacturingsteps never increases only for forming the DTI structure 5.

<n-MIS Region 61/p-MIS Region 62>

As shown in FIG. 5, a p type well region 81 is formed in the epitaxiallayer 12 in the n-MIS region 61. The p type well region 81 is formed,for example, from the surface of the epitaxial layer 12 to a depth thathas a region facing the lower DTI electrode layer 69 with the DTIinsulating film 64 therebetween. An n⁺ type source region 82 and an n⁺type drain region 83 are selectively formed with an intervaltherebetween in the inner region of p type well region 81.

An n-MIS gate electrode 84 is formed on the surface of the epitaxiallayer 12 in the n-MIS region 61 with the surface insulating film 40therebetween. In other words, the surface insulating film 40 formed inthe n-MIS region 61 serves also as an n-MIS gate insulating film 85. Then-MIS gate electrode 84 has its surface covered with a gate surfaceinsulating film 86. The gate surface insulating film 86 may have athickness of, for example, 400 Å.

The impurity concentration of the p type well region 81 may be, forexample, 1.0×10¹⁵ cm⁻³ to 1.0×10¹⁷ cm⁻³. The impurity concentration ofthe n⁺ type source region 82 and that of the n⁺ type drain region 83 maybe each, for example, 1.0×10¹⁸ cm⁻³ to 1.0×10²⁰ cm⁻³.

The region between the n⁺ type source region 82 and the n⁺ type drainregion 83 is an n-MIS channel region 87 of the n-MIS region 61. Thechannel formation in the n-MIS channel region 87 is controlled by then-MIS gate electrode 84. The n-MIS gate electrode 84 is formed so as toface the n-MIS channel region 87 with the n-MIS gate insulating film 85therebetween.

An n type well region 91 is formed in the surface of the epitaxial layer12 in the p-MIS region 62. The n type well region 91 is formed, forexample, from the surface of the epitaxial layer 12 to a depth that hasa region facing the lower DTI electrode layer 69 with the DTI insulatingfilm 64 therebetween. A p⁺ type source region 92 and a p⁺ type drainregion 93 are selectively formed with an interval therebetween in theinner region of the n type well region 91.

A p-MIS gate electrode 94 is formed on the surface of the epitaxiallayer 12 in the p-MIS region 62 with the surface insulating film 40therebetween. In other words, the surface insulating film 40 formed inthe p-MIS region 62 serves also as a p-MIS gate insulating film 95. Thep-MIS gate electrode 94 has its surface covered with the gate surfaceinsulating film 96. The gate surface insulating film 96 may have athickness of, for example, 400 Å.

The impurity concentration of the n type well region 91 may be, forexample, 1.0×10¹⁵ cm⁻³ to 1.0×10¹⁷ cm⁻³. The impurity concentration ofthe p⁺ type source region 92 and that of the p⁺ type drain region 93 maybe each, for example, 1.0×10¹⁸ cm⁻³ to 1.0×10²⁰ cm⁻³.

The region between the p⁺ type source region 92 and the p⁺ type drainregion 93 is a p-MIS channel region 97 of the p-MIS region 62. Thechannel formation in the p-MIS channel region 97 is controlled by thep-MIS gate electrode 94. The p-MIS gate electrode 94 is formed so as toface the p-MIS channel region 97 with the p-MIS gate insulating film 95therebetween.

The interlayer insulating film 42 and the USG film 55 are formed in thisorder in the CMIS region 3 so as to cover the epitaxial layer 12 in thesame way as in the VDMIS region 2 mentioned above.

An n-MIS source contact 100, an n-MIS drain contact 101, an n-MIS gatecontact 102, a p-MIS source contact 103, a p-MIS drain contact 104, anda p-MIS gate contact 105 are formed on the interlayer insulating film 42and the USG film 55. Each contact 100 to 105 has an arrangement in whicha conductor layer is buried in a trench in the same way as theaforementioned gate contact 43 and the like. A specific arrangement ofeach contact 100 to 105 is the same as that of the gate contact 43 andthe like, and therefore a description of the specific arrangement isomitted.

The n-MIS source contact 100 and the p-MIS source contact 103 are formedso as to pass through the interlayer insulating film 42, the USG film55, and the surface insulating film 40 in this order. The n-MIS sourcecontact 100 is connected to the n⁺ type source region 82 exposed fromthe surface of the epitaxial layer 12. On the other hand, the p-MISsource contact 103 is connected to the p⁺ type source region 92 exposedfrom the surface of the epitaxial layer 12. For example, the sourceelectrode film 59 or another source electrode film is connected to then-MIS source contact 100 and to the p-MIS source contact 103, and aground potential is applied thereto.

The n-MIS drain contact 101 and the p-MIS drain contact 104 are formedso as to pass through the interlayer insulating film 42, the USG film55, and the surface insulating film 40 in this order. The n⁺ type drainregion 83 exposed from the surface of the epitaxial layer 12 and a drainelectrode film 107 a formed on the USG film 55 are connected to then-MIS drain contact 101. On the other hand, the p⁺ type drain region 93exposed from the surface of the epitaxial layer 12 and a drain electrodefilm 107 b formed on the USG film 55 are connected to the p-MIS draincontact 104.

The n-MIS gate contact 102 and the p-MIS gate contact 105 are formed soas to pass through the interlayer insulating film 42, the USG film 55,and the gate surface insulating films 86 and 96 in this order. The n-MISgate electrode 84 and a gate electrode film 108 a formed on the USG film55 are connected to the n-MIS gate contact 102. On the other hand, thep-MIS gate electrode 94 and a gate electrode film 108 b formed on theUSG film 55 are connected to the p-MIS gate contact 105.

As described above, the semiconductor device 1 of the present preferredembodiment includes the CMIS region 3 and the passive element region 4that are electrically separated from the VDMIS region 2 by means of theDTI structure 5, in addition to the VDMIS region 2 (see FIG. 1). Thismakes it possible to provide a semiconductor device 1 provided with anIPM (Intelligent Power Module) structure that has excellent reliability.

<Manufacturing Method of Semiconductor Device 1>

FIG. 6A and FIG. 6B are flowcharts to describe one example of amanufacturing process of the VDMIS region 2 and the CMIS region 3according to the semiconductor device 1 of FIG. 1.

Each arrangement according to the VDMIS region 2 and to the CMIS region3 is formed concurrently. As shown in FIG. 6A and FIG. 6B, thesemiconductor substrate 11 is first prepared (step S1), and thenepitaxial growth is performed (step S2), and the epitaxial layer 12 isformed. Thereafter, the gate trench 14 is formed in the VDMIS region 2,and the DTI trench 63 is formed in the CMIS region 3 (step S3).Thereafter, a thermally-oxidized film is formed on the inner surface ofthe gate trench 14 and on the inner surface of the DTI trench 63 (stepS4).

Thereafter, the lower electrode layer 26 is formed at the gate trench14, and the lower DTI electrode layer 69 is formed at the DTI trench 63(step S5). Thereafter, the thermally-oxidized film and the lowerelectrode layer 26 formed at the gate trench 14 are selectively removedin the VDMIS region 2, and the thermally-oxidized film formed on theepitaxial layer 12 in the CMIS region 3 is selectively removed (stepS6). Thereafter, a thermally-oxidized film that serves as the surfaceinsulating film 40, and that serves as the intermediate insulating film24, and that serves as the intermediate DTI insulating film 67 is formedin the VDMIS region 2 and in the CMIS region 3 (step S7). Thereafter,the p type well region 81 and the n type well region 91 are formed inthe CMIS region 3 (step S8).

Thereafter, the upper electrode layer 30 is formed in the gate trench14, and the upper DTI electrode layer 70 is formed in the DTI trench 63(step S9). Thereafter, a thermally-oxidized film that serves as thesecond thin film portion 23 and that serves as the second part 66 isformed on the upper electrode layer 30 and on the upper DTI electrodelayer 70 (step S10). Thereafter, the gate electrode 25 is formed in theCMIS region 3 (step S11). Thereafter, the p type body region 15 and then type drift region 16 are formed in the VDMIS region 2 (step S12).Thereafter, the n⁺ type source region 82 and the n⁺ type drain region 83are formed in the CMIS region 3 (step S13).

Thereafter, the n type source region 17 and the p type contact region 18are formed in the VDMIS region 2 (step S14). Thereafter, the interlayerinsulating film 42 is formed on the epitaxial layer 12 (step S15).Thereafter, the source contact trench 49 passing through the interlayerinsulating film 42 is formed in the VDMIS region 2 (step S16).Thereafter, the gate contact trench 44 passing through the interlayerinsulating film 42 is formed in the VDMIS region 2, and the DTI contacttrench 74 passing through the interlayer insulating film 42 is formed inthe CMIS region 3 (step S17).

Thereafter, the conductor layer 45 is formed at the gate contact trench44 and the source contact trench 49 in the VDMIS region 2, and is formedat the DTI contact trench 74 in the CMIS region 3 (step S18).Thereafter, the USG film 55 is formed on the interlayer insulating film42 (step S19). Thereafter, the source plug 56 is formed so as to passthrough the USG film 55 in the VDMIS region 2, and the DTI plug 76 andeach contact 100 to 105 is formed in the CMIS region 3 (step S20).Thereafter, the source electrode film 59, the drain electrode films 107a and 107 b, and the gate electrode films 108 a and 108 b are formed onthe USG film 55 (step S21).

Hereinafter, a method for manufacturing the semiconductor device 1 willbe described in more detail with reference to FIG. 7A to FIG. 7W andFIG. 8A to FIG. 8W.

FIG. 7A to FIG. 7W are cross-sectional views to describe one example ofa process for manufacturing the VDMIS region 2 according to thesemiconductor device 1 of FIG. 1, corresponding to FIG. 3. FIG. 8A toFIG. 8W are cross-sectional views to describe one example of a processfor manufacturing the CMIS region 3 according to the semiconductordevice 1 of FIG. 1, corresponding to FIG. 5.

As shown in FIG. 7A and FIG. 8A, the n type semiconductor substrate 11is first prepared (step S1). Thereafter, the semiconductor substrate 11undergoes epitaxial growth (step S2). For example, phosphorus (P) thatis an n type impurity is implanted during epitaxial growth. As a result,the n type epitaxial layer 12 is formed on the semiconductor substrate11, and the semiconductor layer 10 is acquired.

Thereafter, the thermally-oxidized film 110 is formed on the surface ofthe epitaxial layer 12 according to a thermal oxidation method. Thethermally-oxidized film 110 may be formed with a thickness of, forexample, 6000 Å. Thereafter, a resist mask (not shown) that selectivelyhas an opening in a region in which the gate trench 14 and the DTItrench 63 are to be formed is formed. An unnecessary part of thethermally-oxidized film 110 is removed by etching (for example, wetetching) by use of the resist mask. Thereafter, the resist mask isremoved.

Thereafter, the epitaxial layer 12 is etched (for example, by dryetching) while using the thermally-oxidized film 110 as a mask. As aresult, the gate trench 14 and the DTI trench 63 are formed (step S3).Thereafter, the thermally-oxidized film 110 is removed by etching (forexample, wet etching).

A shaping step in which the shape of the gate trench 14 and that of theDTI trench 63 are adjusted may be added after the thermally-oxidizedfilm 110 is removed. More specifically, a liner oxide film (not shown)may be formed on the surface of the epitaxial layer 12 including theinner surface of the gate trench 14 and the inner surface of the DTItrench 63 according to the thermal oxidation method. The liner oxidefilm may be formed with a thickness of, for example, 1500 Å. It ispossible to adjust the shape of the gate trench 14 and the shape of theDTI trench 63 by removing the liner oxide film by means of wet etching.

Thereafter, as shown in FIG. 7B and FIG. 8B, the thermally-oxidized film111 is formed on the surface of the epitaxial layer 12 including theinner surface of the gate trench 14 and the inner surface of the DTItrench 63 according to the thermal oxidation method (step S4). Thethermally-oxidized film 111 may be formed with a thickness of, forexample, 3000 Å to 5000 Å. Thereafter, the polysilicon layer 112 isformed so as to backfill the gate trench 14 and the DTI trench 63according to, for example, a CVD (Chemical Vapor Deposition) method(step S5).

Thereafter, as shown in FIG. 7C and FIG. 8C, an unnecessary part of thepolysilicon layer 112 is etchbacked, and the polysilicon layer 112 isburied to a halfway portion in the depth direction of each of the gatetrench 14 and the DTI trench 63. The etchback amount of the polysiliconlayer 112 may be, for example, about 1 μm in the depth direction fromthe opening of the gate trench 14. Thereafter, phosphorus (P) that is ann type impurity is diffused into each polysilicon layer 112 buried inthe gate trench 14 and in the DTI trench 63 according to a so-calledphosphorus-deposit method. At this time, phosphorus is diffused in thedepth direction from the surface of each polysilicon layer 112. As aresult, the lower electrode layer 26 is formed in the VDMIS region 2,and the lower DTI electrode layer 69 is formed in the CMIS region 3.

Thereafter, as shown in FIG. 7D and FIG. 8D, a resist mask 113 withwhich the DTI trench 63 is covered is selectively formed on theepitaxial layer 12 in the CMIS region 3. Thereafter, thethermally-oxidized film 111 formed in the VDMIS region 2 and in the CMISregion 3 is selectively removed by, for example, wet etching by use ofthe resist mask 113 (step S6).

The thermally-oxidized film 111 formed along the inner surface of thegate trench 14 is removed so as to expose the side portion of the lowerelectrode layer 26 in the VDMIS region 2. As a result, in the gatetrench 14, the thermally-oxidized film 111 remains as the thick filmportion 21 of the gate insulating film 20. At this time, a part of theupper end portion of the lower electrode layer 26 may be removed. On theother hand, in the CMIS region 3, the thermally-oxidized film 111remains in the DTI trench 63 as the first part 65 of the DTI insulatingfilm 64. Thereafter, the resist mask 113 is removed.

Thereafter, as shown in FIG. 7E and FIG. 8E, the surface insulating film40 that is a thermally-oxidized film is formed on the surface of theepitaxial layer 12 including the inner surface of each of the gatetrench 14 and the DTI trench 63 according to the thermal oxidationmethod (step S7). The surface insulating film 40 may be formed with athickness of, for example, 250 Å. In the VDMIS region 2, theintermediate insulating film 24 is formed on the surface of the lowerelectrode layer 26. Furthermore, the upper end portion 28 that has theconvex portion 29 is formed at the lower electrode layer 26 inaccordance with the formation of the intermediate insulating film 24(see FIG. 4 also). On the other hand, in the CMIS region 3, theintermediate DTI insulating film 67 is formed on the surface of thelower DTI electrode layer 69. At this time, the intermediate insulatingfilm 24 and the intermediate DTI insulating film 67 may be formedthicker than the surface insulating film 40.

Thereafter, as shown in FIG. 7F and FIG. 8F, an ion implanting mask 115that selectively has an opening 115 a in a region in which the p typewell region 81 is to be formed is formed on the epitaxial layer 12.Thereafter, a p type impurity is implanted through the opening 115 a ofthe ion implanting mask 115. The implantation of the p type impurity isperformed through the surface insulating film 40. The ion implantingmask 115 is removed after the p type impurity is implanted.

Thereafter, as shown in FIG. 7G and FIG. 8G, another ion implanting mask116 that selectively has an opening 116 a in a region in which the ntype well region 91 is to be formed is formed on the epitaxial layer 12.Thereafter, an n type impurity is implanted through the opening 116 a ofthe ion implanting mask 116. The implantation of the n type impurity isperformed through the surface insulating film 40. The ion implantingmask 116 is removed after the n type impurity is implanted. Thereafter,annealing is applied, and the p type well region 81 and the n type wellregion 91 are formed in the CMIS region 3 (step S8).

Thereafter, as shown in FIG. 7H and FIG. 8H, the polysilicon layer 117is deposited so as to backfill the gate trench 14 and the DTI trench 63according to, for example, the CVD method (step S9). In the VDMIS region2, the polysilicon layer 117 is formed so as to backfill the gate trench14 from above the intermediate insulating film 24. On the other hand, inthe CMIS region 3, the polysilicon layer 117 is formed so as to backfillthe DTI trench 63 from above the intermediate DTI insulating film 67.

Thereafter, as shown in FIG. 7I and FIG. 8I, an unnecessary part of thepolysilicon layer 117 is etchbacked, and the polysilicon layer 117 isburied in the gate trench 14 and in the DTI trench 63. Thereafter,phosphorus (P) that is an n type impurity is diffused into eachpolysilicon layer 117 buried in the gate trench 14 and in the DTI trench63 according to the so-called phosphorus-deposit method. At this time,phosphorus is diffused in the depth direction from the surface of eachpolysilicon layer 117. As a result, the upper electrode layer 30 isformed in the VDMIS region 2, whereas the upper DTI electrode layer 70is formed in the CMIS region 3.

Thereafter, as shown in FIG. 7J and FIG. 8J, the second thin filmportion 23 serving as the gate insulating film 20 is formed so as tocover the upper electrode layer 30, and the second part 66 serving asthe DTI insulating film 64 is formed so as to cover the upper DTIelectrode layer 70 according to, for example, the thermal oxidationmethod (step S10). As a result, in the VDMIS region 2, the trench gatestructure 19 in which the gate electrode 25 (the lower electrode layer26 and the upper electrode layer 30) is buried in the gate trench 14 isacquired. On the other hand, in the CMIS region 3, a structure in whichthe DTI electrode 68 (the lower DTI electrode layer 69 and the upper DTIelectrode layer 70) is buried in the DTI trench 63 is acquired.

Thereafter, as shown in FIG. 7K and FIG. 8K, a polysilicon layer 118 isformed on the epitaxial layer 12 according to, for example, the CVDmethod (step S11). Thereafter, phosphorus (P) that is an n type impurityis diffused into the polysilicon layer 118 according to the so-calledphosphorus-deposit method. At this time, phosphorus is diffused in thedepth direction from the surface of the polysilicon layer 118.

Thereafter, as shown in FIG. 7L and FIG. 8L, an unnecessary part of thepolysilicon layer 118 is removed, and the n-MIS gate electrode 84 andthe p-MIS gate electrode 94 are formed in the CMIS region 3. Thereafter,the gate surface insulating films 86 and 96 are formed so as to coverthe surface of each of the n-MIS gate electrode 84 and the p-MIS gateelectrode 94 according to, for example, the thermal oxidation method.The gate surface insulating films 86 and 96 may be formed with athickness of, for example, 400 Å.

Thereafter, as shown in FIG. 7M and FIG. 8M, an ion implanting mask 119by which the VDMIS region 2 is exposed is formed so as to cover the CMISregion 3. Thereafter, boron (B) that is a p type impurity is implantedin a multistage manner (in this step, two-stage implantation) throughthe ion implanting mask 119. The p type impurity is implanted, and thenphosphorus (P) that is an n type impurity is implanted in a multistagemanner (in this step, two-stage implantation) continuously through theion implanting mask 119 at a position deeper than a region into whichthe p type impurity has been implanted. The ion implanting mask 119 isremoved after the n type impurity is implanted. Thereafter, annealing isapplied, and the p type body region 15 and the n type drift region 16are formed (step S12).

Thereafter, in the CMIS region 3, an ion implanting mask (not shown)that selectively has an opening is formed on the epitaxial layer 12 in aregion in which the n⁺ type source region 82 and the n⁺ type drainregion 83 are to be formed. Thereafter, an n type impurity is implantedthrough the ion implanting mask. The ion implanting mask is removedafter the n type impurity is implanted.

The ion implanting mask is removed, and then another ion implanting mask(not shown) that selectively has an opening in a region in which the p⁺type source region 92 and the p⁺ type drain region 93 are to be formedis formed. Thereafter, a p type impurity is implanted through this ionimplanting mask. The ion implanting mask is removed after the p typeimpurity is implanted. Thereafter, annealing is applied, and the n⁺ typesource region 82, the n⁺ type drain region 83, the p⁺ type source region92, and the p⁺ type drain region 93 are formed in the CMIS region 3(step S13).

Thereafter, as shown in FIG. 7N and FIG. 8N, an ion implanting mask 120that selectively exposes the VDMIS region 2 is formed on the epitaxiallayer 12. Thereafter, arsenic (As) that is an n type impurity isimplanted through the ion implanting mask 120. The n type impurity isimplanted, and then the ion implanting mask 120 is removed. Thereafter,annealing is applied, and the n type source region 17 is formed in theVDMIS region 2.

Thereafter, an ion implanting mask (not shown) that selectively exposesa region in which the p type contact region 18 (see FIG. 2) is to beformed is formed on the epitaxial layer 12. Thereafter, boron (B) thatis a p type impurity is implanted through this ion implanting mask. Thep type impurity is implanted, and then the ion implanting mask isremoved. Thereafter, annealing is applied, and the p type contact region18 is formed in the VDMIS region 2 (step S14).

Thereafter, as shown in FIG. 7O and FIG. 8O, the interlayer insulatingfilm 42 made of silicon nitride is formed on the epitaxial layer 12according to, for example, the CVD method (step S15). If needed, thesurface of the interlayer insulating film 42 may be flattened after thisstep. The flattening of the interlayer insulating film 42 may be carriedout through the following step. For example, a USG film (not shown) isformed on the interlayer insulating film 42 according to the CVD method.Thereafter, according to a CMP (Chemical Mechanical Polishing) method,the USG film is ground until the surface of the interlayer insulatingfilm 42 is exposed. As a result, a rugged state generated in theinterlayer insulating film 42 is backfilled by the USG, and the surfaceof the interlayer insulating film 42 is flattened.

Thereafter, as shown in FIG. 7P and FIG. 8P, a resist mask 121 thatselectively has an opening 121 a in a region in which the source contacttrench 49 is to be formed is formed on the interlayer insulating film 42(step S16). Thereafter, the interlayer insulating film 42, the surfaceinsulating film 40, and the epitaxial layer 12 (the n type source region17, the p type contact region 18, and the p type body region 15) areselectively removed according to dry etching through the resist mask 121(for example, according to a RIE (Reactive Ion Etching) method). As aresult, the source contact trench 49 is formed. Thereafter, boron (B)that is a p type impurity is selectively implanted along the innersurface of the source contact trench 49 from which the p type bodyregion 15 is exposed while using the resist mask 121 as an ionimplanting mask. At this time, the p type impurity may be implanted bydiagonal irradiation with respect to the inner surface of the sourcecontact trench 49. As a result, the p type extra contact region 51 isformed. The p type extra contact region 51 is formed, and then theresist mask 121 is removed.

Thereafter, as shown in FIG. 7Q and FIG. 8Q, a resist mask 122 thatselectively has an opening 122 a in a region in which the gate contacttrench 44 and the DTI contact trench 74 are to be formed is formed onthe interlayer insulating film 42 (step S17). At this time, the resistmask 122 is formed on the interlayer insulating film 42 so as tobackfill the source contact trench 49.

Thereafter, as shown in FIG. 7R and FIG. 8R, the interlayer insulatingfilm 42, the second thin film portion 23 of the gate insulating film 20(the second part 66 of the DTI insulating film 64), the upper electrodelayer 30 (the upper DTI electrode layer 70), the intermediate insulatingfilm 24 (the intermediate DTI insulating film 67), and the lowerelectrode layer 26 (the lower DTI electrode layer 69) are removed inthis order according to dry etching (for example, the RIE method)through the resist mask 122.

This five-layer etching is performed while appropriately changing thekind of etching gas. As a result, in the VDMIS region 2, the gatecontact trench 44 that has a bottom portion passing through theintermediate insulating film 24 and reaching the upper end portion 28(the convex portion 29) of the lower electrode layer 26 is formed. Onthe other hand, in the CMIS region 3, the DTI contact trench 74 that hasa bottom portion passing through the intermediate DTI insulating film 67and reaching the lower DTI electrode layer 69 is formed. The gatecontact trench 44 and the DTI contact trench 74 are formed, and then theresist mask 122 is removed.

Thereafter, as shown in FIG. 7S and FIG. 8S, a conductor layer 123 isformed so as to backfill each contact trench 44, 49, and 74 and so as tocover the interlayer insulating film 42 (step S18). In a step of formingthe conductor layer 123, a first conductor layer 124 including titaniumor titanium nitride is first formed along the inner surface of eachcontact trench 44, 49, and 74 and along the surface of the interlayerinsulating film 42 according to, for example, the CVD method.Thereafter, each contact trench 44, 49, and 74 is backfilled, and thesecond conductor layer 125 including tungsten with which the interlayerinsulating film 42 is covered is formed according to, for example, theCVD method. As a result, the conductor layer 123 including the firstconductor layer 124 and the second conductor layer 125 is formed.

Thereafter, as shown in FIG. 7T and FIG. 8T, an unnecessary part of theconductor layer 45 formed on the interlayer insulating film 42 excludingeach contact trench 44, 49, and 74 is removed by etchback. As a result,the conductor layers 45, 50, and 75 are buried in the contact trenches44, 49, and 74, respectively, and the gate contact 43, the sourcecontact 48, and the DTI contact 73 are formed.

Thereafter, as shown in FIG. 7U and FIG. 8U, the USG film 55 is formedon the interlayer insulating film 42 so as to cover each contact 43, 48,and 73 (step S19). Thereafter, a resist mask 126 that selectively has anopening 126 a in a region in which the source plug 56, the DTI plug 76,and each contact 100 to 105 (see FIG. 5 also) are to be formed is formedon the USG film 55 (step S20). Thereafter, the plug trench 57, the DTIplug trench 77, and trenches for each contact 100 to 105 are formedaccording to dry etching through the resist mask 126 (for example, theRIE method). Thereafter, the resist mask 126 is removed.

Thereafter, as shown in the FIG. 7V and the FIG. 8V, a conductor layeris embedded in each trench according to the same method as in the stepof forming the conductor layers 45, 50, and 75. As a result, the sourceplug 56, the DTI plug 76, and each contact 100 to 105 are formed.

Thereafter, as shown in the FIG. 7W and the FIG. 8W, an electrode filmincluding an AlCu film is formed on the USG film 55 so as to cover thesource plug 56, the DTI plug 76, and each contact 100 to 105 accordingto, for example, a plating method (step S21). Thereafter, the electrodefilm is selectively removed, and is separated into the source electrodefilm 59, each drain electrode film 107 a and 107 b, and each gateelectrode film 108 a and 108 b. Thereafter, the drain electrode 60 isformed on the reverse surface of the semiconductor substrate 11. Thesemiconductor device 1 is formed through these steps.

According to the aforementioned method, the source contact trench 49that is comparatively shallow is formed (step S16: see FIG. 7P and FIG.8P), and then the gate contact trench 44 and the DTI contact trench 74that are deeper than the source contact trench 49 are formed (step S17:see FIG. 7R and FIG. 8R).

In a case in which the source contact trench 49 that is comparativelyshallow is formed after the gate contact trench 44 and the DTI contacttrench 74 that are comparatively deep are formed, the resist mask 122must be formed so as to backfill the gate contact trench 44 and the DTIcontact trench 74 that are comparatively deep. Additionally, the resistmask 122 must be removed from the gate contact trench 44 and from theDTI contact trench 74 after the source contact trench 49 is formed.Therefore, the manufacturing process becomes not only difficult but alsolong in time required to perform the process.

Therefore, it is possible to avoid a step of burying and removing theresist mask 122 in and from the comparatively deep gate contact trench44 and the comparatively deep DTI contact trench 74 by previouslyforming the comparatively shallow source contact trench 49. As a result,it is possible to accurately form the source contact trench 49, the gatecontact trench 44, and the DTI contact trench 74, and, in addition, itis possible to shorten the duration of time required in themanufacturing process.

Second Preferred Embodiment

FIG. 9 is a schematic cross-sectional view of a semiconductor device 130according to a second preferred embodiment of the present invention. Thesemiconductor device 130 differs from the aforementioned semiconductordevice 1 in the fact that an IGBT region 131 is formed instead of theVDMIS region 2. A main arrangement of the semiconductor device 130 isthe same as that of the semiconductor device 1 (see FIG. 3 also). InFIG. 9, the same reference sign as in FIG. 1 to FIG. 8W is given to acomponent corresponding to each component of FIG. 1 to FIG. 8W mentionedabove, and a description of this component is omitted.

As shown in FIG. 9, the semiconductor device 130 has the semiconductorlayer 10 including a p⁺ type semiconductor substrate 132 instead of then⁺ type semiconductor substrate 11. The semiconductor device 130additionally has an n type emitter region 133 and an emitter electrodefilm 134 instead of the n type source region 17 and the source electrodefilm 59 of the VDMIS region 2. The n type emitter region 133 is oneexample of the first conductivity type region of the present invention.It is also possible to fulfill the same effect as the semiconductordevice 1 by means of the semiconductor device 130 including the IGBTregion 131 as described above.

Third Preferred Embodiment

FIG. 10 is an enlarged cross-sectional view showing the trench gatestructure 19 of the semiconductor device 135 according to a thirdpreferred embodiment of the present invention. The semiconductor device135 according to the third preferred embodiment differs from thesemiconductor device 1 in the fact that a gate electrode 136 is formedinstead of the gate electrode 25 and in the fact that a gate contact 137is formed instead of the gate contact 43. In the other respects, thesemiconductor device 135 is arranged in the same way as thesemiconductor device 1 (see FIG. 3 also). In FIG. 10, the same referencesign as in FIG. 1 to FIG. 9 is given to a component corresponding toeach component of FIG. 1 to FIG. 9 mentioned above, and a description ofthis component is omitted.

As shown in FIG. 10, the gate electrode 136 includes a lower electrodelayer 138 and an upper electrode layer 139 that are separated upwardlyand downwardly from each other by means of the intermediate insulatingfilm 24. The upper end portion 28 of the lower electrode layer 138includes a convex portion 140. The upper end portion 28 may be arrangedso as to be regarded as not having the convex portion 140 by forming theconvex portion 140 of the lower electrode layer 138 with substantiallythe same width as the other parts of the lower electrode layer 138(width W1≈width W2).

The intermediate insulating film 24 is formed along the convex portion140 of the lower electrode layer 138 so as to be integrally continuouswith the thick film portion 21 and the first thin film portion 22 of thegate insulating film 20. The upper electrode layer 139 has a lower endportion 141 facing the convex portion 140 (the upper end portion 28) ofthe lower electrode layer 138 with the intermediate insulating film 24therebetween. The upper electrode layer 139 is formed so as to overlapwith the convex portion 140 of the lower electrode layer 26.

The gate contact 137 is formed so as to pass through the interlayerinsulating film 42, the second thin film portion 23 of the gateinsulating film 20, the upper electrode layer 139, and the intermediateinsulating film 24 in this order and so as to reach the lower electrodelayer 138. The gate contact 137 has a side portion contiguous to theinterlayer insulating film 42, to the second thin film portion 23 of thegate insulating film 20, to the upper electrode layer 139, to theintermediate insulating film 24, and to the lower electrode layer 138and a bottom portion contiguous to the convex portion 140 (the upper endportion 28) of the lower electrode layer 26.

The gate contact 137 has a trench contact structure that includes a gatecontact trench 142 having a tapered shape in which the width of anopening becomes narrower from the opening toward the bottom portion whenviewed cross-sectionally and the conductor layer 45 buried in this gatecontact trench 142.

The gate contact trench 142 is formed by digging down the interlayerinsulating film 42, the second thin film portion 23 of the gateinsulating film 20, the upper electrode layer 139, and the intermediateinsulating film 24 in this order so as to reach the lower electrodelayer 138. The gate contact trench 142 has a side portion from which theinterlayer insulating film 42, the second thin film portion 23 of thegate insulating film 20, the upper electrode layer 139, the intermediateinsulating film 24, and the lower electrode layer 138 are exposed and abottom portion from which the lower electrode layer 138 is exposed.

With respect to the direction perpendicular to the depth direction ofthe gate trench 14, the bottom portion of the gate contact trench 142has a width W3 smaller than a width W1 of the upper end portion 28(parts other than the convex portion 140) of the lower electrode layer138. More specifically, the bottom portion of the gate contact trench142 has a width W3 smaller than a width W2 of the convex portion 140 ofthe lower electrode layer 138. The width of the opening of the gatecontact trench 142 may be smaller than the width W1 of the upper endportion 28 of the lower electrode layer 138, or may be greater than thewidth W1 of the upper end portion 28 of the lower electrode layer 138.

As described above, it is possible to fulfill the same effects as thesemiconductor device 1 also by means of the semiconductor device 135.Additionally, it is possible to excellently electrically connect(short-circuit) the upper electrode layer 139 and the lower electrodelayer 138 together by positioning the bottom portion of the gate contact137 at a depth lower than the intermediate insulating film 24.

It is possible to embody the present invention in other modes althoughthe modes according to the preferred embodiments of the presentinvention have been described as above.

For example, an arrangement shown in FIG. 11 may be employed althoughthe trench gate structure 19 is formed in a stripe manner as describedin each preferred embodiment mentioned above. FIG. 11 is a schematicperspective cross-sectional view of a semiconductor device 143 accordingto a first modification.

Of course, the arrangement of the semiconductor device 143 is alsoapplicable to the arrangement according to the semiconductor device 130of the second preferred embodiment and applicable to the arrangementaccording to the semiconductor device 135 of the third preferredembodiment although the semiconductor device 143 is shown as amodification of the semiconductor device 1 according to the firstpreferred embodiment in FIG. 11. In FIG. 11, the same reference sign isgiven to an arrangement common to that of the semiconductor device 1,and a description of this arrangement is omitted.

As shown in FIG. 11, the trench gate structure 19 may have a gate trench14 formed in a grid-shaped manner when viewed planarly. In other words,a plurality of unit cells 13 may be formed so as to be arranged in asquare matrix. Each unit cell 13 is defined by a single square-matrixregion that is partitioned by the straight line passing through thecenter of the trench gate structure 19 when viewed planarly.

The gate contact 43 is formed in a grid-shaped manner, when viewedplanarly, along the longitudinal direction of the gate trench 14. Thesource contact 48 (the source contact trench 49) is formed in aquadrangular region surrounded by the gate trench 14 when viewedplanarly. The n type source region 17 and the p type contact region 18are selectively formed in a region between the side portion of thesource contact trench 49 and the side portion of the gate trench 14, notshown in FIG. 11. The other arrangements are the same as those of thesemiconductor device 1.

Additionally, an arrangement shown in FIG. 12 may be employed althoughthe gate contacts 43 and 137 are formed in a stripe manner along thetrench gate structure 19 as described in each of the aforementionedpreferred embodiments. FIG. 12 is a schematic perspectivecross-sectional view of a semiconductor device 144 according to a secondmodification.

Of course, the arrangement of the semiconductor device 144 is alsoapplicable to the arrangement according to the semiconductor device 130of the second preferred embodiment and applicable to the arrangementaccording to the semiconductor device 135 of the third preferredembodiment although the semiconductor device 144 is shown as amodification of the semiconductor device 1 according to the firstpreferred embodiment in FIG. 12. In FIG. 12, the same reference sign isgiven to an arrangement common to that of the semiconductor device 1,and a description of this arrangement is omitted.

As shown in FIG. 12, the gate contact 43 may include a plurality of gatecontact holes 145 formed so as to be spaced out and conductor layers 45buried in the gate contact holes 145, respectively, along the stripedirection of the gate trench 14. The gate contact hole 145 may bepolygonal when viewed planarly, i.e., may be quadrangular when viewedplanarly or may be hexagonal when viewed planarly. Additionally, thegate contact hole 145 may be circular or elliptical when viewedplanarly.

Additionally, as shown in FIG. 12, the source contact 48 may include aplurality of source contact holes 146 formed so as to be spaced out andconductor layers 50 buried in the source contact holes 146,respectively, along the stripe direction of the gate trench 14 althoughthe source contact 48 is formed in a stripe manner as described in eachof the aforementioned preferred embodiments. Of course, each arrangementof the gate contact holes 145 and each arrangement of the source contactholes 146 may be applied to each arrangement of the DTI contact 73, thesource plug 56, the DTI plug 76, and the contacts 100 to 105.

When an arrangement, such as that of the gate contact holes 145 and thatof the source contact holes 146, is applied, an area that functions as aheat dissipation material becomes smaller with respect to the gatecontact 43, the source contact 48, and the like. Therefore, it can besaid that the arrangement according to the first to third preferredembodiments is more desirable.

Additionally, an arrangement shown in FIG. 13 may be employed althoughthe gate contact 43 (the gate contact trench 44) has the bottom portioncontiguous to the convex portion 29 of the lower electrode layer 26 asdescribed in the first and second preferred embodiments. FIG. 13 is aschematic enlarged cross-sectional view showing the trench gatestructure 19 of a semiconductor device 147 according to a thirdmodification.

Of course, the arrangement of the semiconductor device 147 is alsoapplicable to the arrangement according to the semiconductor device 130of the second preferred embodiment although the semiconductor device 147is shown as a modification of the semiconductor device 1 according tothe first preferred embodiment in FIG. 13. In FIG. 13, the samereference sign is given to an arrangement common to that of thesemiconductor device 1, and a description of this arrangement isomitted.

As shown in FIG. 13, the gate contact trench 44 is formed by diggingdown the interlayer insulating film 42, the second thin film portion 23of the gate insulating film 20, the upper electrode layer 30, and theintermediate insulating film 24 in this order so as to reach the lowerelectrode layer 26. The gate contact trench 44 has a side portion fromwhich the interlayer insulating film 42, the second thin film portion 23of the gate insulating film 20, the upper electrode layer 30, theintermediate insulating film 24, and the lower electrode layer 26 areexposed and a bottom portion from which the lower electrode layer 26 isexposed. This arrangement also makes it possible to fulfill the sameeffects as the semiconductor device 1.

Additionally, the gate insulating film 20 may be formed with a uniformthickness although the gate insulating film 20 includes the thick filmportion 21 and the first thin film portion 22 as described in each ofthe aforementioned preferred embodiments. If so, the gate insulatingfilm 20 may have an arrangement shown in FIG. 14. FIG. 14 is a schematicenlarged cross-sectional view showing the trench gate structure 19 of asemiconductor device 148 according to a fourth modification.

Of course, the arrangement of the semiconductor device 148 is alsoapplicable to the arrangement according to the semiconductor device 130of the second preferred embodiment and applicable to the arrangementaccording to the semiconductor device 135 of the third preferredembodiment although the semiconductor device 148 is shown as amodification of the semiconductor device 1 according to the firstpreferred embodiment in FIG. 14. In FIG. 14, the same reference sign isgiven to an arrangement common to that of the semiconductor device 1,and a description of this arrangement is omitted.

As shown in FIG. 14, the gate insulating film 20 does not have the firstthin film portion 22, and includes the thick film portion 21 formedalong the whole area of the inner surface of the gate trench 14.According to this arrangement, in the manufacturing process, it ispossible to exclude the step of selectively removing thethermally-oxidized film 111 formed in the gate trench 14 and the lowerelectrode layer 26 (step S6) (see FIG. 7D and the like). As a result, itis possible to simplify the manufacturing process, and hence is possibleto shorten the period of time required in the manufacturing process.However, the side portion 33 of the upper electrode layer 30 faces the ptype body region 15 with the thick film portion 21 therebetween, andtherefore, in consideration of channel controllability, it can be saidthat the arrangement of each of the aforementioned preferred embodimentsis more desirable.

Of course, the gate insulating film 20 does not have the thick filmportion 21, and may be arranged so as to include the first thin filmportion 22 formed along the whole area of the inner surface of the gatetrench 14. If so, channel controllability is improved while acapacitance value in a lower part of the gate trench 14 (the trench gatestructure 19) is increased, and therefore, it can be said that thearrangement of each of the aforementioned preferred embodiments is moredesirable.

Additionally, the gate trench 14 and the DTI trench 63 may have atapered shape in which the width of an opening becomes narrower from theopening toward the bottom portion when viewed cross-sectionally althougheach of the gate trench 14 and the DTI trench 63 has the side portionperpendicular to the surface of the epitaxial layer 12 as described ineach of the aforementioned preferred embodiments.

Additionally, the gate contact trench 44 may have a tapered shape inwhich the width of an opening becomes narrower from the opening towardthe bottom portion when viewed cross-sectionally although the gatecontact trench 44 has the side portion perpendicular to the surface ofthe epitaxial layer 12 as described in the first and second preferredembodiments.

Additionally, the source contact trench 49 may have a tapered shape inwhich the width of an opening becomes narrower from the opening towardthe bottom portion when viewed cross-sectionally although the sourcecontact trench 49 has the side portion perpendicular to the surface ofthe epitaxial layer 12 as described in each of the aforementionedpreferred embodiments.

Additionally, the source contact trench 49 may have a bottom portioncontiguous to the n type source region 17 without passing through the ptype body region 15 or a bottom portion contiguous to the surface of theepitaxial layer 12 from which the n type source region 17 is exposedwithout passing through the p type body region 15 although the sourcecontact trench 49 having the bottom portion in the p type body region 15is formed as described in each of the aforementioned preferredembodiments.

Additionally, in each of the aforementioned preferred embodiments, thegate trench 14 and the source contact trench 49 may be formed with thesame depth. In this case, the gate trench 14 and the source contacttrench 49 may be formed through the same step.

Additionally, although an example in which the DTI structure 5 is formedin a square annular shape when viewed planarly has been described ineach of the aforementioned preferred embodiments, the present inventionis not limited to this example if the CMIS region 3 and the passiveelement region 4 are electrically separable from the VDMIS region 2.Therefore, the DTI structure 5 may be formed in an annular shape whenviewed planarly or in an elliptic annular shape when viewed planarly, ormay be formed in a polygonal annular shape when viewed planarly, such asa triangular shape when viewed planarly or a hexagonal shape when viewedplanarly.

Additionally, the DTI structure 5 may be formed so as to surround theperiphery of the VDMIS region 2 although the DTI structure 5 is formedso as to surround the periphery of the CMIS region 3 and the peripheryof the passive element region 4 as described in each of theaforementioned preferred embodiments. In this case, either the CMISregion 3 or the passive element region 4 is not necessarily required tobe surrounded by the DTI structure 5.

Additionally, a semiconductor device that has characteristics of boththe VDMIS (MISFET) and the IGBT may be manufactured by combining thefirst and second preferred embodiments together so as to form thesemiconductor substrate 11 that has both the n⁺ type impurity region andthe p⁺ type impurity region.

Additionally, in the semiconductor devices 1, 130, 135, 143, 144, 147,148 mentioned above, an arrangement in which the conductivity type ofeach semiconductor part is reversed may be employed. In other words, thep type part may be an n type, and the n type part may be a p type.

Additionally, in each of the aforementioned preferred embodiments, a BJT(Bipolar Junction Transistor) region, a JFET (Junction Field EffectTransistor) region, or a nonvolatile memory region that has a controlgate and a floating gate may be formed instead of the CMIS region 3.Additionally, all or some of these regions may be selectively formed onthe epitaxial layer 12. Additionally, an integrated circuit, such as LSI(Large Scale Integration), SSI (Small Scale Integration), MSI (MediumScale Integration), VLSI (Very Large Scale Integration), or ULSI(Ultra-Very Large Scale Integration), may be arranged by combining theseregions together.

Additionally, the aforementioned semiconductor devices 1, 130, 135, 143,144, 147, and 148 may be mounted in a semiconductor package. If so, theexamples shown in FIG. 15 to FIG. 21 may be employed.

FIG. 15 is an upper-surface perspective view showing one example of asemiconductor package 151 in which the semiconductor device 1, 130, 135,143, 144, 147, or 148 is mounted. FIG. 16 is a plan view showing aninternal structure of the semiconductor package 151 shown in FIG. 15.FIG. 17 is a cross-sectional view taken along line XVII-XVII shown inFIG. 16. Hereinafter, the aforementioned semiconductor device 1, 130,135, 143, 144, 147, or 148 is referred to simply as a “semiconductorchip 150.”

As shown in FIG. 15 to FIG. 17, the semiconductor package 151 includeslead frames 152 a and 152 b to which the semiconductor chip 150 isconnected, a plurality of (in this example, four) input terminals 153 ato 153 d that form outer terminals and that supply electric power to thesemiconductor chip 150 from the outside, a plurality of (in thisexample, four) output terminals 154 a to 154 d that form outer terminalsand that output an electric signal acquired from the semiconductor chip150 to the outside, and a package body 155 that seals the semiconductorchip 150, the lead frames 152 a and 152 b, a part of the input terminals153 a to 153 d, and a part of the output terminals 154 a to 154 d.

As shown in FIG. 15, the package body 155 is formed in, for example, asubstantially rectangular shape of about 4 mm×5 mm. The package body 155has a pair of first side portion 155 a and second side portion 155 balong the longitudinal direction of the package body 155. The packagebody 155 includes sealing resin such as epoxy resin.

As shown in FIG. 16, the pair of lead frames 152 a and 152 b each ofwhich is substantially rectangular are disposed in the package body 155when the surface of the package body 155 is viewed from the normaldirection (hereinafter, referred to simply as “when viewed planarly”).The lead frames 152 a and 152 b are disposed with an intervaltherebetween along the longitudinal direction of the package body 155 soas to be electrically separated from each other. Each of the lead frames152 a and 152 b has an area that is greater than the area of thesemiconductor chip 150 when viewed planarly.

As shown in FIG. 17, the semiconductor chip 150 is a verticalsemiconductor device that has the drain electrode 60 (see FIG. 3 also)serving as a back-surface electrode on the reverse surface side. Thedrain electrode 60 of each semiconductor chip 150 is connected to thecorresponding lead frames 152 a and 152 b through a solder 156. Eachsemiconductor chip 150 is connected so as to be installed in thecorresponding lead frames 152 a and 152 b.

As shown in FIG. 15 and FIG. 16, each input terminal 153 a to 153 d isdisposed on the side of the first side portion 155 a of the package body155. The input terminals 153 a to 153 d are spaced out along thelongitudinal direction of the first side portion 155 a so as to beelectrically separated from each other. Furthermore, each input terminal153 a to 153 d is disposed with an interval from each of the lead frames152 a and 152 b so as to be electrically separated from each of the leadframes 152 a and 152 b.

As shown in FIG. 16, the input terminal 153 a and the input terminal 153b form a pair of input terminals with respect to the semiconductor chip150 connected to the lead frame 152 a disposed on one side. Likewise,the input terminal 153 c and the input terminal 153 d form a pair ofinput terminals with respect to the semiconductor chip 150 connected tothe lead frame 152 b disposed on the other side.

Each of the input terminals 153 a and 153 c is electrically connected tothe source pad 6 disposed in the VDMIS region 2 of the correspondingsemiconductor chip 150 through a bonding wire 157. In other words, theinput terminal 153 a and the input terminal 153 c form a ground terminalto which a ground potential is applied. On the other hand, each of theinput terminals 153 b and 153 d is electrically connected to the CMISregion 3 of the corresponding semiconductor chip 150 through a bondingwire 157.

Every one of the input terminals 153 a to 153 d integrally has an innerlead 158 disposed in the package body 155 and an outer lead 159 disposedoutside the package body 155.

Each inner lead 158 includes a flat plate portion 160 that has a flatsurface formed substantially horizontally with respect to the surface ofeach of the lead frames 152 a and 152 b. Each flat plate portion 160 ispositioned above the surface of each of the lead frames 152 a and 152 b(on the surface side of the package body 155). Each flat plate portion160 may have a flat surface that is substantially flush with the surfaceof the semiconductor chip 150 (the surface on the side on which thedrain electrode 60 is not formed). Each flat plate portion 160 iselectrically connected to each semiconductor chip 150 through a bondingwire 157.

A comparatively large voltage is applied to the VDMIS region 2. From theviewpoint of restraining or preventing the increase of the resistancevalue, the input terminal 153 a and the input terminal 153 c may beelectrically connected to the corresponding semiconductor chip 150through a plurality of (two or more) bonding wires 157. Additionally,instead of a plurality of bonding wires 157, one thick wire that has awire diameter corresponding to the total value of each wire diameter ofthe plurality of bonding wires 157, a conductor plate, or the like maybe used. The bonding wire 157, the thick wire, the conductor plate, orthe like may include any one of, for example, gold (Au), copper (Cu),aluminum (Al), or an alloy of these elements.

On the other hand, each outer lead 159 includes an extension portion 161that extends from the inner lead 158 toward the reverse surface side ofthe package body 155 and a lower end portion 162 that extends from thelower end of the extension portion 161 in the direction opposite to thepackage body 155. The lower end portion 162 of the outer lead 159 ispositioned below the reverse surface of the package body 155, and isconnected to a wire or the like disposed on a mounting substrate or thelike by means of, for example, a solder. Electric power input from theoutside into the outer lead 159 is supplied to the semiconductor chip150 through the inner lead 158 and through the bonding wire 157.

On the other hand, as shown in FIG. 15 to FIG. 17, each output terminal154 a to 154 d is disposed on the side of the second side portion 155 bof the package body 155. The output terminals 154 a to 154 d are spacedout along the longitudinal direction of the second side portion 155 b.

The output terminal 154 a and the output terminal 154 b form a pair ofdrain terminals electrically connected to the drain electrode 60 of thesemiconductor chip 150 through the lead frame 152 a and the solder 156that are disposed on one side. Likewise, the output terminal 154 c andthe output terminal 154 d form a pair of drain terminals electricallyconnected to the drain electrode 60 of the semiconductor chip 150through the lead frame 152 b and the solder 156 that are disposed on theother side.

As shown in FIG. 16, every one of the output terminals 154 a to 154 dintegrally has an inner lead 163 disposed in the package body 155 and anouter lead 164 disposed outside the package body 155.

As shown in FIG. 17, each inner lead 163 is positioned above the surfaceof each of the lead frames 152 a and 152 b (on the surface side of thepackage body 155). Each inner lead 163 is formed so as to be integrallycontinuous with the corresponding lead frames 152 a and 152 b through aconnection portion 165 extending toward the reverse surface side of thepackage body 155 in the package body 155. The inner lead 163 iselectrically connected to the semiconductor chip 150 through theconnection portion 165, the lead frame 152, and the solder 156.

On the other hand, each outer lead 164 includes an extension portion 166that extends from the inner lead 163 toward the reverse surface side ofthe package body 155 and a lower end portion 167 that extends from thelower end of the extension portion 166 in the direction opposite to thepackage body 155. The lower end portion 167 of the outer lead 164 ispositioned so as to be flush with the lower end portion 162 of eachinput terminal 153 a to 153 d, and is connected to a wire or the likedisposed on the mounting substrate or the like by means of, for example,a solder. An electric signal acquired from the semiconductor chip 150 isoutput to the outside from the outer lead 164 through the solder 156,the lead frame 152, and the inner lead 163.

Referring again to FIG. 15, the package body 155 has its surface havingan index 168 that determines a mounting direction. The index 168 may bea concave portion that is hollowed toward the reverse surface side ofthe package body 155, or may be a mark attached to the surface of thepackage body 155. In this example, a concave portion is formed as theindex 168. The index 168 is formed at a corner portion of the surface ofthe package body 155 positioned near the input terminal 153 a whenviewed planarly. This makes it possible to indicate the position of theinput terminal 153 a, and makes it possible to determine the mountingdirection of the semiconductor package 151.

According to this arrangement, it is possible to provide a two-channelsemiconductor package 151 whose semiconductor chip 150 is connected toeach of the pair of lead frames 152 a and 152 b.

The semiconductor chips 150 connected to each of the lead frames 152 aand 152 b may be the same as each other in specifications, or may differfrom each other in specifications so as to have, for example, differentinput voltages and different output signals. Additionally, although thetwo-channel semiconductor package 151 has been described in thisexample, a multichannel (three-channel or more) semiconductor packagemay be employed. Additionally, a one-channel semiconductor package maybe employed. If the one-channel semiconductor package is employed, anexample shown in FIG. 18 may be employed.

FIG. 18 is an upper-surface perspective view showing a semiconductorpackage 171 in which the semiconductor chip 150 is mounted. FIG. 19 isan undersurface perspective view of the semiconductor package 171 shownin FIG. 18. FIG. 20 is a plan view showing an internal structure of thesemiconductor package 171 shown in FIG. 18. FIG. 21 is a cross-sectionalview taken along line XXI-XXI shown in FIG. 20.

The semiconductor package 171 differs from the semiconductor package 151in the fact that the semiconductor package 171 is a one-channel type, inthe fact that the semiconductor package 171 includes one lead frame 172instead of the pair of lead frames 152 a and 152 b, in the fact that thesemiconductor package 171 includes input terminals 173 a to 173 dinstead of the input terminals 153 a to 153 d, in the fact that thesemiconductor package 171 includes output terminals 174 a to 174 dinstead of the output terminals 154 a to 154 d, and in the fact that thesemiconductor package 171 includes a package body 175 instead of thepackage body 155. In the other respects, the semiconductor package 171is arranged in the same way as the aforementioned semiconductor package151. In FIG. 18 to FIG. 21, the same reference sign as in FIG. 15 toFIG. 17 is given to a component corresponding to each component of FIG.15 to FIG. 17 mentioned above, and a description of this component isomitted.

As shown in FIG. 18 to FIG. 21, the package body 175 is formed in, forexample, a substantially rectangular shape of about 3 mm×3 mm. As shownin FIG. 20, the lead frame 172 that is substantially rectangular isdisposed in the package body 175 when the surface of the package body175 is viewed from the normal direction (hereinafter, referred to simplyas “when viewed planarly”). The drain electrode 60 of the semiconductorchip 150 is connected to the upper surface of the lead frame 172 throughthe solder 156. On the other hand, as shown in FIG. 19 and FIG. 21, anundersurface 172 a of the lead frame 172 is exposed from theundersurface of the package body 175. The undersurface 172 a of the leadframe 172 may be exposed so as to protrude from the undersurface of thepackage body 175 as shown in FIG. 19. The undersurface 172 a of the leadframe 172 may be exposed so as to be hollowed toward the inner part ofthe package body 175 rather than be exposed from the undersurface of thepackage body 175.

Each input terminal 173 a to 173 d is disposed on the side of the sideportion 175 a on one side of the package body 175. The input terminals173 a to 173 d are spaced out along the longitudinal direction of theside portion 175 a on the other side so as to be electrically separatedfrom each other. Furthermore, each input terminal 173 a to 173 d isdisposed with an interval from the lead frame 172 so as to beelectrically separated from the lead frame 172.

A part of the upper portion of each input terminal 173 a to 173 d and apart of its side portion positioned on the side of the lead frame 172are sealed by the package body 175. On the other hand, the bottomportion of each input terminal 173 a to 173 d and its side portionpositioned on the side opposite to the lead frame 172 are exposed from acorner portion at which the side portion 175 a on the one side of thepackage body 175 and the undersurface of the package body 175 intersecteach other. Each input terminal 173 a to 173 d may be exposed so as toprotrude from the undersurface of the package body 175 as shown in FIG.19. Each input terminal 173 a to 173 d may be exposed so as to behollowed toward the inner part of the package body 175 rather than beexposed from the undersurface of the package body 175.

The input terminal 173 a is electrically connected to the source pad 6disposed in the VDMIS region 2 of the semiconductor chip 150 through thebonding wire 157. In other words, the input terminal 173 a forms aground terminal to which a ground potential is applied. On the otherhand, the input terminal 173 c is electrically connected to the CMISregion 3 of the semiconductor chip 150 through the bonding wire 157. Theexposed portion of each input terminal 173 a to 173 d is connected to awire or the like disposed on a mounting substrate or the like by meansof, for example, a solder. Electric power input from the outside intoeach input terminal 173 a to 173 d is supplied to the semiconductor chip150 through the bonding wire 157.

Although the input terminal 173 b and the input terminal 173 d areelectrically opened in this example, each of the input terminals 173 band 173 d may be electrically connected to the VDMIS region 2 or to theCMIS region 3 through the bonding wire 157. Additionally, the inputterminal 173 b may be formed integrally with the input terminal 173 a orwith the input terminal 173 c in the package body 175. Additionally, theinput terminal 173 d may be formed integrally with the input terminal173 c in the package body 175.

On the other hand, each output terminal 174 a to 174 d is disposed onthe side of the side portion 175 b that is on the other side facing theside portion 175 a that is on the one side of the package body 175 withthe lead frame 172 therebetween. The output terminals 174 a to 174 d arespaced out along the longitudinal direction of the side portion 175 b onthe other side.

A part of the upper portion of each output terminal 174 a to 174 d and apart of its side portion positioned on the side of the lead frame 172are sealed by the package body 175. On the other hand, the bottomportion of each output terminal 174 a to 174 d and its side portionpositioned on the side opposite to the lead frame 172 are exposed from acorner portion at which the side portion 175 b on the other side of thepackage body 175 and the undersurface of the package body 175 intersecteach other. Each output terminal 174 a to 174 d may be exposed so as toprotrude from the undersurface of the package body 175 as shown in FIG.19. Each output terminal 174 a to 174 d may be exposed so as to behollowed toward the inner part of the package body 175 rather than beexposed from the undersurface of the package body 175.

Each output terminal 174 a to 174 d is formed so as to be integrallycontinuous with the lead frame 172 through, for example, a connectionportion 176 in the package body 175. An electric signal acquired fromthe semiconductor chip 150 is output to the outside from each outputterminal 174 a to 174 d through the lead frame 172 and through theconnection portion 176. Each output terminal 174 a to 174 d may beelectrically connected to the lead frame 172 through, for example, abonding wire instead of the connection portion 176. Any one of theoutput terminals 174 a to 174 d may be electrically separated from thelead frame 172.

Referring again to FIG. 18, the package body 175 has its surface havingan index 177 that determines a mounting direction. The index 177 isformed at a corner portion of the surface of the package body 175positioned near the input terminal 173 a when viewed planarly. Thismakes it possible to indicate the position of the input terminal 173 a,and makes it possible to determine the mounting direction of thesemiconductor package 171.

According to this arrangement, it is possible to provide a one-channelsemiconductor package 171 whose single semiconductor chip 150 isconnected to the single lead frame 172. Additionally, according to thesemiconductor package 171, the undersurface 172 a of the lead frame 172is exposed from the undersurface of the package body 175, and thereforeit is possible to effectively dissipate heat generated in thesemiconductor chip 150 to the outside. In consideration of thesemiconductor package 151, the semiconductor package 171 may be formedas a multichannel (two-channel or more) semiconductor package.

The aforementioned semiconductor chip 150 (the semiconductor device 1,130, 135, 143, 144, 147, 148) and the semiconductor packages 151 and 171are capable of being incorporated into a power module for use in aninverter circuit forming a driving circuit to drive an electric motorthat is used as a power source of, for example, an electric automobile(including a hybrid automobile), a train, and an industrial robot.Additionally, the semiconductor chip 150 and the semiconductor packages151 and 171 are also capable of being incorporated into a power modulefor use in an inverter circuit that converts electric power generated bya solar battery, by a wind generator, or by other power generators(particularly, a private electric generator) so as to match the electricpower of a commercial power source.

Besides, various design changes can be made within the scope of thematters recited in the appended claims.

What is claimed is:
 1. A semiconductor device comprising: asemiconductor layer in which a gate trench is formed; a gate insulatingfilm formed along an inner surface of the gate trench; a gate electrodethat is buried in the gate trench through the gate insulating film andthat has a lower electrode and an upper electrode that are separatedupwardly and downwardly from each other with an intermediate insulatingfilm between the lower electrode and the upper electrode; and an openingconnecting the lower electrode and the upper electrode together.
 2. Thesemiconductor device according to claim 1, wherein the lower electrodeincludes a convex portion protruding toward the opening side of the gatetrench, and the convex portion is electrically connected with the upperelectrode.
 3. The semiconductor device according to claim 1, wherein theupper electrode includes a central portion and a peripheral portionsurrounding the central portion at a bottom of the upper electrode, andthe central portion is positioned at a shallower level than theperipheral portion.
 4. The semiconductor device according to claim 1,wherein the upper electrode has a width wider than that of the lowerelectrode.
 5. The semiconductor device according to according to claim1, further comprising a gate contact is formed in the opening and is incontact with the lower electrode and the upper electrode.
 6. Thesemiconductor device according to claim 1, further comprising: a secondconductivity type body region formed at a surface portion of thesemiconductor layer; and a first conductivity type region formed in thebody region, wherein the gate insulating film includes: a thick filmportion contiguous to the lower electrode; and a thin film portion thatis smaller in thickness than the thick film portion and that isinterposed between the upper electrode and the body region.
 7. Thesemiconductor device according to claim 6, wherein the thin film portionof the gate insulating film has a thickness of 1/10 or less with respectto the thick film portion of the gate insulating film.
 8. Thesemiconductor device according to claim 6, further comprising a contactfor use in the first conductivity type region, the contact being formedso as to pass through the first conductivity type region and so as toreach the body region.
 9. The semiconductor device according to claim 8,wherein the contact for use in the first conductivity type region isformed along the longitudinal direction of the gate trench.
 10. Thesemiconductor device according to claim 8, wherein the contact for usein the first conductivity type region includes tungsten.
 11. Thesemiconductor device according to claim 1, wherein the semiconductorlayer includes an element region electrically separated by a DTI (DeepTrench Isolation) structure, the DTI structure comprising: a DTIinsulating film formed along an inner surface of a DTI trench formed inthe semiconductor layer; a DTI electrode that is buried in the DTItrench through the DTI insulating film and that has a lower DTIelectrode and an upper DTI electrode that are separated upwardly anddownwardly from each other with the DTI intermediate insulating filmbetween the lower DTI electrode and the upper DTI electrode; and a DTIcontact that is formed in the DTI trench so as to pass through the upperDTI electrode and through the DTI intermediate insulating film and so asto reach the lower DTI electrode and that electrically connects thelower DTI electrode and the upper DTI electrode together.
 12. Thesemiconductor device according to claim 11, wherein a ground potentialis applied to the DTI contact.
 13. The semiconductor device according toclaim 11, wherein the element region includes a CMIS (Complementary MIS)region, the CMIS region having a first conductivity type MISFET(Metal-Insulator-Semiconductor Field-Effect Transistor) and a secondconductivity type MISFET.
 14. A method for manufacturing a semiconductordevice, the method comprising: a step of forming a gate trench in asemiconductor layer; a step of forming a gate insulating film along aninner surface of the gate trench; a step of forming a lower electrode byburying a conductive material to a halfway portion in a depth directionof the gate trench; a step of forming an intermediate insulating film bycoating the lower electrode with an insulating film; a step of formingan upper electrode by burying a conductive material so as to backfillthe gate trench from above the intermediate insulating film; and a stepof forming an opening so as to connect the lower electrode and the upperelectrode together by allowing the opening to pass through the upperelectrode and through the intermediate insulating film and to reach thelower electrode.
 15. The method for manufacturing the semiconductordevice according to claim 14, further comprising a step of forming agate contact in the opening so as to contact the lower electrode and theupper electrode.
 16. The method for manufacturing the semiconductordevice according to claim 14, the method further comprising: a step of,prior to a step of forming the intermediate insulating film, allowingthe gate insulating film contiguous to the lower electrode to remain asa thick film portion by selectively removing the gate insulating film tothe halfway portion in the depth direction of the gate trench; the stepof forming the intermediate insulating film including a step of formingthe insulating film that has a thickness smaller than the thick filmportion along the inner surface of the gate trench from which the gateinsulating film has been removed and forming a thin film portion servingas the gate insulating film; a step of forming a body region facing theupper electrode with the thin film portion of the gate insulating filmbetween the body region and the upper electrode by implanting a secondconductivity type impurity into a surface portion of the semiconductorlayer; and a step of forming a first conductivity type region byimplanting a first conductivity type impurity into a surface portion ofthe semiconductor layer in the body region.
 17. The method formanufacturing the semiconductor device according to claim 16, the methodfurther comprising a step of forming a contact for the firstconductivity type region, the contact passing through the firstconductivity type region and reaching the body region.
 18. The methodfor manufacturing the semiconductor device according to claim 17,wherein the contact for the first conductivity type region is formed,the contact including tungsten.